CAT524
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
FEATURES
s
Four 8-bit DPPs configured as programmable
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Single supply operation: 2.7V - 5.5V
s
Setting read-back without effecting outputs
voltage sources in DAC-like applications
s
Common reference inputs
s
Buffered wiper outputs
s
Non-volatile NVRAM memory wiper storage
s
Output voltage range includes both supply rails
s
4 independently addressable buffered
APPLICATIONS
s
Automated product calibration
s
Remote control adjustment of equipment
s
Offset, gain and zero adjustments in
output wipers
s
1 LSB accuracy, high resolution
s
Serial Microwire-like interface
self-calibrating and adaptive control systems
s
Tamper-proof calibrations
s
DAC (with memory) substitute
DESCRIPTION
The CAT524 is a quad, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
The four independently programmable DPPs have an
output range which includes both supply rails. The
wipers are buffered by rail to rail op amps. Wiper
settings, stored in non-volatile NVRAM memory, are not
lost when the device is powered down and are
automatically reinstated when power is returned. Each
wiper can be dithered to test new output values without
FUNCTIONAL DIAGRAM
RDY/BSY
3
V
DD
1
V
REFH
14
24kΩ(4)
PROG
7
PROGRAM
CONTROL
effecting the stored settings, and stored settings can be
read back without disturbing the DPP’s output.
The CAT524 is controlled with a simple 3-wire serial,
Microwire-like interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the Tri-Stated CAT524 Data
Output pin. A RDY/BSY output working in concert with
an internal low voltage detector signals proper operation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT524 is available in the 0˚C to 70˚C commercial
and -40˚C to 85˚C industrial operating temperature
ranges. Both 14-pin plastic DIP and SOIC packages are
offered.
PIN CONFIGURATION
DIP Package (P, L)
+
–
13
V
OUT1
SOIC Package (J, W)
VDD
CLK
RDY/BSY
CS
DI
DO
PROG
1
2
3
14
13
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREFL
GND
VDD
DI
5
WIPER
CONTROL
REGISTERS
AND
NVRAM
1
2
3
14
13
12
CLK
+
–
12
V
OUT2
VREFH
VOUT1
VOUT2
VOUT3
VOUT4
VREFL
GND
RDY/BSY
CS
DI
DO
PROG
CLK
2
SERIAL
CONTROL
+
–
11
CAT
4
11
524
5
10
12
CAT
11
4
524
5
10
6
7
9
8
CS
4
V
OUT3
6
7
9
8
+
–
10
VOUT4
SERIAL
DATA
OUTPUT
REGISTER
6
DO
CAT524
8
GND
9
V
REFL
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 2006, Rev. E
CAT524
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
V
DD
to GND
Inputs
CLK to GND
CS to GND
DI to GND
RDY/BSY to GND
PROG to GND
V
REF
H to GND
V
REF
L to GND
Outputs
D
0
to GND
V
OUT
1– 4 to GND
-0.5V to +7V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
-0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix)
0°C to +70°C
Industrial (‘I’ suffix)
-40°C to +85°C
Junction Temperature
+150°C
Storage Temperature
-65°C to +150°C
Lead Soldering (10 sec max)
+300°C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
RELIABILITY CHARACTERISTICS
Symbol
V
ZAP(1)
I
LTH(1)(2)
Parameter
ESD Susceptibility
Latch-Up
Min
2000
100
Max
Units
Volts
mA
Test Method
MIL-STD-883, Test Method 3015
JEDEC Standard 17
NOTES:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
POWER SUPPLY
Symbol Parameter
I
DD1
I
DD2
Supply Current (Read)
Supply Current (Write)
Conditions
Normal Operating
Programming, V
DD
= 5V
V
DD
= 3V
V
DD
Operating Voltage Range
Min
—
—
—
2.7
Typ
400
1600
1000
—
Max
600
2500
1600
5.5
Units
µA
µA
µA
V
LOGIC INPUTS
Symbol
I
IH
I
IL
V
IH
V
IL
Parameter
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
Conditions
V
IN
= V
DD
V
IN
= 0V
Min
—
—
2
0
Typ
—
—
—
—
Max
10
-10
V
DD
0.8
Units
µA
µA
V
V
LOGIC OUTPUTS
Symbol Parameter
V
OH
V
IL
High Level Output Voltage
Low Level Output Voltage
Conditions
I
OH
= -40µA
I
OL
= 1 mA, V
DD
= +5V
I
OL
= 0.4 mA, V
DD
= +3V
Min
V
DD
-0.3
—
—
Typ
—
—
—
Max
—
0.4
0.4
Units
V
V
V
Doc. No. 2006, Rev. E
2
CAT524
POTENTIOMETER CHARACTERISTICS
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Symbol
R
POT
Parameter
Potentiometer Resistance
R
POT
to R
POT
Match
Pot Resistance Tolerance
Voltage on V
REFH
pin
Voltage on V
REFL
pin
Resolution
INL
DNL
R
OUT
I
OUT
TC
RPOT
C
H
/C
L
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Potentiometer Capacitances
300
8/8
2.7
0V
0.4
0.5
0.25
1
0.5
10
3
Conditions
See Note 3
—
Min
Typ
24
+0.5
+1
+20
V
DD
V
DD
- 2.7
Max
Units
kΩ
%
%
V
V
%
LSB
LSB
Ω
mA
ppm/˚C
pF
AC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Symbol
Digital
t
CSMIN
t
CSS
t
CSH
t
DIS
t
DIH
t
DO1
t
DO0
t
HZ
t
LZ
t
BUSY
t
PS
t
PROG
t
CLK
H
t
CLK
L
f
C
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
DPP Settling Time to 1 LSB
150
100
0
50
50
—
—
—
—
—
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
3
6
—
—
—
—
—
150
150
—
—
5
—
—
—
—
1
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
µs
µs
Parameter
Conditions
Min
Typ
Max
Units
C
L
=100pF,
see note 1
Analog
t
DS
C
LOAD
= 10 pF, V
DD
= +5V
C
LOAD
= 10 pF, V
DD
= +3V
NOTES:
1. All timing measurements are defined at the point of signal crossing V
DD
/ 2.
2. These parameters are periodically sampled and are not 100% tested.
3. The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between V
REFH
and
V
REFL
of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ
+20% value.
3
Doc. No. 2006, Rev. E
TIMING
MIN/MAX
FROM
TO
CAT524
A. C. TIMING DIAGRAM
Doc. No. 2006, Rev. E
to
2
3
4
5
1
PARAM
NAME
t CLK H
t CLK H
Rising CLK edge to falling CLK edge
Min
CLK
t CLK L
Falling CLK edge to CLK rising edge
Min
Min
t CSH
t CLK L
t CSS
t CSH
Falling CLK edge for last data bit (DI)
to falling CS edge
Rising CS edge to next rising CLK edge
t CSS
Min
CS
t CSMIN
t CSMIN
Falling CS edge to rising CS edge
t DIS
Data valid to first rising CLK
edge after CS = high
Min
Min
t DIS
DI
t DIH
t DO0
t LZ
t DO0
Rising CLK edge to end of data valid
Min
t DIH
4
t HZ
t DO1
t HZ
t PS
t PS
t PROG
t BUSY
3
4
5
Rising CLK edge to D0 = low
Rising CS edge to D0 becoming high
low impedance (active output)
Max
(Max)
t LZ
DO
Rising CLK edge to D0 = high
Falling CS edge to D0 becoming high
impedance (Tri-State)
Max
(Max)
t DO1
PROG
Rising PROG edge to next rising
CLK edge
t PROG
Rising PROG edge to falling
PROG edge
t BUSY
Falling CLK edge after PROG=H to
rising RDY/BSY edge
Min
Min
RDY/BSY
Max
to
1
2
CAT524
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DPP addressing is as follows:
Function
Power supply positive.
Clock input pin.Clock input pin.
Ready/Busy Output
Chip Select
Serial data input pin.
Serial data output pin.
Non-volatile Memory Programming
Enable Input
Power supply ground.
Minimum DPP output voltage.
DPP output channel 4.
DPP output channel 3.
DPP output channel 2.
DPP output channel 1.
Maximum DPP output voltage.
Name
V
DD
CLK
RDY/BSY
CS
DI
DO
PROG
GND
V
REFL
V
OUT4
V
OUT3
V
OUT2
V
OUT1
V
REFH
DPP OUTPUT
V
OUT1
V
OUT2
V
OUT3
V
OUT4
A0
0
1
0
1
A1
0
0
1
1
DEVICE OPERATION
The CAT524 is a quad 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost when
power is removed from the chip. Upon power up the
DPPs return to the settings stored in non-volatile memory.
Each DPP can be written to and read from independently
without effecting the output voltage during the read or
write cycle. Each output can also be temporarily adjusted
without changing the stored output setting, which is
useful for testing new output settings before storing
them in memory.
DIGITAL INTERFACE
The CAT524 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT524’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT524’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT524’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
5
Doc. No. 2006, Rev. E
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
