CAT24C208
8-Kb Dual Port Serial EEPROM
FEATURES
I
Supports Standard and Fast I
2
C protocol*
I
2.5V to 5.5V operation
I
16-byte page write buffer
I
Schmitt triggers and noise protection filters
DESCRIPTION
The CAT24C208 is an 8-Kbit Dual Port Serial CMOS
EEPROM internally organized as 4 segments of 256
bytes each. The CAT24C208 features a 16-byte page
write buffer and can be accessed from either of two
separate I
2
C compatible ports, DSP (SDA, SCL) and
DDC (SDA, SCL).
Arbitration between the two interface ports is automatic
and allows the appearance of individual access to the
memory from each interface.
on I
2
C bus input
I
Low power CMOS technology
I
1,000,000 program/erase cycles
I
100 year data retention
I
Industrial temperature range
I
RoHS-compliant 8-lead SOIC package
For Ordering Information details, see page 12.
BLOCK DIAGRAM
DSP VCC
ARBITRATION
LOGIC
DDC VCC
DSP SCL
DSP SDA
DISPLAY
CONTROL
LOGIC
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
D
E
C
O
D
E
R
S
DDC
CONTROL
LOGIC
DDC SCL
DDC SDA
VSS
CONFIGURATION
REGISTER
EDID SEL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1044, Rev. F
1
CAT24C208
PIN CONFIGURATION
SOIC (W)
DSP VCC
DSP SCL
DSP SDA
VSS
1
2
3
4
8
7
6
5
DDC VCC
EDID SEL
DDC SCL
DDC SDA
PIN DESCRIPTION
Pin Number
1
2
Pin Name
DSP V
CC
DSP SCL
Function
Device power from display controller
The CAT24C208 DSP serial clock bidirectional pin is used to clock all
data transfers into or out of the device DSP SDA pin and is also used to
block DSP Port access when DDC Port is active.
DSP Serial Data/Address. The bidirectional DSP serial data/address pin
is used to transfer data into and out of the device from a display
controller. The DSP SDA pin is an open drain output and can be wire-
OR'ed with other open drain or open collector outputs.
Device ground.
DDC Serial Data/Address. The bidirectional DDC serial data/address
pin is used to transfer data into and out of the device from a DDC host.
The DDC SDA pin is an open drain output and can be wire-OR'ed with
other open drain or open collector outputs.
The CAT24C208 DDC serial clock bidirectional pin is used to clock all
data transfers into or out of the device DDC SDA pin, and is used to
block DDC Port for access when DSP Port is active.
EDID select. The CAT24C208 EDID select input selects the active bank
of memory to be accessed via the DDC SDA/SCL interface as set in
the configuration register.
Device power when powered from a DDC host.
3
DSP SDA
4
5
V
SS
DDC SDA
6
DDC SCL
7
EDID SEL
8
DDC V
CC
Doc. No. 1044, Rev. F
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C208
ABSOLUTE MAXIMUM RATINGS
(1)
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
............ -2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ................ -2.0V to +7.0V
Reliability Characteristics
Symbol
N
END(4)
T
DR(4)
V
ZAP(4)
I
LTH(4)(5)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
Volts
mA
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100mA
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008
JEDEC Standard JESD 22
JEDEC Standard 17
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= 2.5V to 5.5V, unless otherwise specified.
Symbol Parameter
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
V HY S
V
OL1
V
CCL1
V
CCL2
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Hysteresis
Output Low Voltage (V
CC
= 3V)
Leakage DSP V
CC
to DDC V
CC
Leakage DDC V
CC
to DSP V
CC
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or either
DSP or DDC V
CC
V
IN
= GND to either
DSP or DDC V
CC
V
OUT
= GND to either
DSP or DDC V
CC
Min
Typ
Max
3
50
10
10
Units
mA
µA
µA
µA
V
V
V
– 1
V
CC
x 0.7
0.05
I
OL
= 3 mA
V
CC
x 0.3
V
CC
+ 0.5
0.4
+100
+100
V
µA
µA
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1044, Rev. F
CAT24C208
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Parameter
Input/Output Capacitance (Either DSP or DDC SDA)
Input Capacitance (EDID, Either DSP or DDC SCL)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
V
CC
= 2.5V to 5.5V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission
Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start
Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.3
0.6
1.3
0.6
0.6
0
100
300
300
Min
Max
400
100
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Power-Up Timing(1)(2)
Symbol
t
PUR
t
PUW
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does
not respond to its slave address.
Doc. No. 1044, Rev. F
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C208
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I
2
C interface
ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL), and with the use of segment pointer at
address 60h. On power up and after any instruction, the
segment pointer will be in segment 00h for DSP and in
segment 00h of the bank selected by the configuration
register for DDC.
The entire memory appears as contiguous memory
space from the perspective of the display interface
(DSP_SDA and DSP_SCL), see Table 2, and Figures
11 to Figure 18 for a complete description of the DSP
Interface.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device
as seen from the DDC interface, (DDC_SDA and
DDC_SCL).
Read and write operations can be performed on any
location within the memory space from the display DSP
interface regardless of the state of the EDID SEL pin or
the activity on the DDC interface. From the DDC
interface, the memory space appears as two 512 byte
banks of memory, with 2 segments each 00h and 01h in
the upper and lower bank, see Table 1.
Each bank of memory can be used to store an E-EDID
data structure. However, only one bank can be read
through the DDC port at a time. The active bank of
memory (that is, the bank that appears at address A0h
on the DDC port) is controlled through the configuration
register at 62/63h and the EDID_SEL pin.
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the
device configuration register at device address 62h.
The device automatically arbitrates between the two
interfaces to allow the appearance of individual access
to the memory from each interface.
In a typical E-EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual-mode (analog and digital)
display. In this manner, the E-EDID appearing at ad-
dress A0h on the DDC port will be either the analog or
digital E-EDID, depending on the state of the “Analog
Cable Detect” pin (pin C3 of the M1-DA connector). See
Figure 1.
+5V DC
(SUPPLIED
BY DISPLAY)
10K
8
7
6
5
E-EDID
EEPROM
1
2
3
4
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
M1-DA CONNECTOR
Figure 1.
28
DDC +5V
47.5K
C3
27
26
DDC CLK
DDC DATA
TO HOST
CONTROLLER
FUSE, RESISTOR
OR OTHER CURRENT
LIMITING DEVICE
REQUIRED IN ALL M1 DISPLAYS
8
HPD
2A MAX
RELAY CONTACTS SHOWN IN
DE-ENERGIZED POSITION
Table 1: DDC Interface
Table 2: DSP Interface
MEMORY ARRAY
01
Upper
Bank
00
01
Lower
Bank
00
Segment 1
256 Bytes
Segment 0
256 Bytes
Segment 1
256 Bytes
00
11
10
01
00
MEMORY ARRAY
Segment 3
256 Bytes
Segment 2
256 Bytes
Segment 1
256 Bytes
Segment 0
256 Bytes
00
00
Segment 0
256 Bytes
Segment Pointer
Address by
No Segment Pointer
Configuration Register
(see Figure 19)
5
Segment Pointer
No Segment Pointer
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1044, Rev. F
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