CAT24C164
FEATURES
16-Kb CMOS Serial EEPROM, Cascadable
DEVICE DESCRIPTION
The CAT24C164 is a 16-Kb CMOS cascadable Serial
EEPROM device organized internally as 128 pages of
16 bytes each, for a total of 2048x8 bits. The device
supports both the Standard (100 kHz) as well as Fast
(400 kHz) I
2
C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C164 devices on the same bus.
■
Supports Standard and Fast I
2
C Protocol
■
1.8 V to 5.5 V Supply Voltage Range
■
16-Byte Page Write Buffer
■
Hardware Write Protection for entire memory
■
Schmitt Triggers and Noise Suppression Filters
on
I
2
C
Bus Inputs (SCL and SDA).
■
Low power CMOS technology
■
1,000,000 program/erase cycles
■
100 year data retention
■
Industrial temperature range
■
RoHS-compliant 8-lead PDIP, SOIC, TSSOP and
8-pad TDFN packages.
For Ordering Information details, see page 15.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (VP2)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0
WP
CAT24C164
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
VSS
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1118, Rev. A
CAT24C164
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
-65°C to +150°C
-0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
1
1
1
1
V
CC
x 0.3
Units
mA
mA
μA
μA
V
V
V
V
V
CC
x 0.7 V
CC
+ 0.5
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN(3)
C
IN(3)
I
WP(5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH,
V
CC
= 5.5 V
V
IN
< V
IH,
V
CC
= 3.3 V
V
IN
< V
IH,
V
CC
= 1.8 V
V
IN
> V
IH
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Max
8
6
200
150
100
1
Units
pF
pF
μA
Doc. No. 1118, Rev. A
2
CAT24C164
POWER-ON RESET (POR)
CAT24C164 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24C164 device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular Slave device it is requesting. The most
significant bit of the 8-bit slave address is fixed as 1. (see
Figure 2). The next three significant bits (A2, A1, A0)
are the device address bits and define which device or
which part of the device the Master is accessing (The
A1 bit must be the compliment of the A1 input pin signal).
Up to eight CAT24C164 devices may be individually ad-
dressed by the system. The next three bits are used as
the three most significant bits of the data word address.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9
th
clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
The CAT24C164 can be made compatible with the
CAT24C16 by tying A2, A1 and A0 to V
SS
or by leaving
A2, A1 and A0 float.
WP:
The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C164 supports the Inter-Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C164
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver.
Doc. No. 1118, Rev. A
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
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