UNISONIC TECHNOLOGIES CO., LTD
UF840
8A, 500V, 0.85Ω, N-CHANNEL
POWER MOSFET
DESCRIPTION
The N-Channel enhancement mode silicon gate power MOSFET
is designed for high voltage, high speed power switching
applications such as switching regulators, switching converters,
solenoid, motor drivers, relay drivers.
1
MOSFET
TO-220
FEATURES
* 8A, 500V, Low R
DS(ON)
(0.85Ω)
* Single Pulse Avalanche Energy Rated
* Rugged - SOA is Power Dissipation Limited
* Fast Switching Speeds
* Linear Transfer Characteristics
* High Input Impedance
1
TO-220F
*Pb-free plating product number: UF840L
SYMBOL
D
G
S
ORDERING INFORMATION
Order Number
Package
Normal
Lead Free Plating
UF840-TA3-T
UF840L-TA3-T
TO-220
UF840-TF3-T
UF840L-TF3-T
TO-220F
Note: Pin Assignment: G: GATE D: DRAIN S: SOURCE
Pin Assignment
1
2
3
G
D
S
G
D
S
Packing
Tube
Tube
UF840L-TA3-T
(1)Packing Type
(2)Package Type
(3)Lead Plating
(1) T: Tube
(2) TA3: TO-220, TF3: TO-220F
(3) L: Lead Free Plating, Blank: Pb/Sn
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UF840
ABSOLUTE MAXIMUM RATINGS
(Ta = 25
℃
, unless Otherwise Specified.)
PARAMETER
Drain to Source Voltage (T
J
=25
℃
~125
℃
)
Drain to Gate Voltage (R
GS
= 20kΩ, T
J
=25
℃
~125
℃
)
Gate to Source Voltage
Continuous
Tc = 100
℃
Drain Current
Pulsed
SYMBOL
V
DSS
V
DGR
V
GS
I
D
I
DM
RATINGS
500
500
±20
8.0
5.1
32
125
1.0
MOSFET
UNIT
V
V
V
A
A
A
W
W/
℃
Total Power Dissipation (Ta = 25
℃)
P
D
Derating above 25
℃
Single Pulse Avalanche Energy Rating
E
AS
510
mJ
(V
DD
=50V, starting T
J
=25
℃
, L=14mH, R
G
=25Ω, peak I
AS
= 8A)
Operating Temperature Range
T
OPR
-55 ~ +150
℃
Storage Temperature Range
T
STG
-55 ~ +150
℃
Note: 1.Signified recommend operating range that indicates conditions for which the device is intended to be
functional, but does not guarantee specific performance limits.
2.Absolute maximum ratings indicate limits beyond which damage to the device may occur.
THERMAL DATA
PARAMETER
Thermal Resistance Junction-Ambient
Thermal Resistance Junction-Case
SYMBOL
θ
JA
θ
Jc
RATINGS
62.5
1.0
UNIT
℃
/W
ELECTRICAL SPECIFICATIONS
(T
a
=25
℃
, unless Otherwise Specified.)
PARAMETER
SYMBOL
TEST CONDITIONS
Drain to Source Breakdown Voltage
BV
DSS
I
D
= 250µA, V
GS
= 0V (Figure 16)
Gate to Threshold Voltage
V
GS(THR)
V
GS
= V
DS
, I
D
= 250µA
On-State Drain Current (Note 1)
I
D(ON)
V
DS
> I
D(ON)
x R
DS(ON)MAX
, V
GS
= 10V
V
DS
= Rated BV
DSS
, V
GS
= 0V
Zero Gate Voltage Drain Current
I
DSS
V
DS
=0.8xRated BV
DSS
,V
GS
=0V,T
J
= 125
℃
Gate to Source Leakage Current
I
GSS
V
GS
= ±20V
Drain to Source On Resistance
R
DS(ON)
I
D
= 4.4A, V
GS
= 10V (Figure 14, 15)
(Note 1)
Forward Transconductance (Note 1)
g
FS
V
DS
≥
50V, I
D
= 4.4A (Figure 18)
Turn-On Delay Time
t
DLY(ON)
V
DD
=250V, I
D
≈
8A, R
G
= 9.1Ω, R
L
=30Ω
Rise Time
t
R
Turn-Off Delay Time
t
DLY(OFF)
(Note 2)
Fall Time
t
F
Total Gate Charge
Q
G(TOT)
V
GS
=10V, I
D
=8A,V
DS
=0.8 x Rated BV
DSS
I
G(REF)
=1.5mA (Figure 20)
Gate to Source Charge
Q
GS
(Note 3)
Gate to Drain “Miller” Charge
Q
GD
Input Capacitance
C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1.0MHz
Output Capacitance
C
OSS
(Figure 17)
Reverse - Transfer Capacitance
C
RSS
NOTE : 1. Pulse Test: Pulse width≤300µs, Duty Cycle≤2%.
2. MOSFET Switching Times are Essentially Independent of Operating Temperature.
3. Gate Charge is Essentially Independent of Operating Temperature.
MIN
500
2
8
TYP MAX UNIT
V
4
V
A
25
µA
250
µA
±100 nA
0.8
4.9
7.4
15
21
50
20
42
7
22
1225
200
85
0.85
21
35
74
30
63
Ω
S
ns
ns
ns
ns
nC
nC
nC
pF
pF
pF
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UF840
INTERNAL PACKAGE INDUCTANCE
PARAMETER
SYMBOL
MIN
TYP
3.5
4.5
7.5
Internal Drain Inductance
Measured from the contact screw on tab to center of die
L
D
Measured from the drain lead(6mm from package) to center of die
Internal Source Inductance
L
S
Measured from the source lead(6mm from header) to source bond pad
Remark:
Modified MOSFET symbol showing the internal devices inductances as below.
D
L
D
G
L
S
S
MOSFET
MAX
UNIT
nH
nH
nH
SOURCE TO DRAIN DIODE SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Source to Drain Diode Voltage
T
J
= 25
℃
, I
SD
= 8.0A, V
GS
= 0V(Figure 19)
V
SD
(Note 1)
Continuous Source to Drain Current
I
SD
Note 2
Pulse Source to Drain Current
I
SDM
T
J
= 25
℃
, I
SD
= 8.0A, dI
SD
/dt = 100A/µs
Reverse Recovery Time
t
RR
210
T
J
= 25
℃
, I
SD
= 8.0A, dI
SD
/dt = 100A/µs
Reverse Recovery Charge
Q
RR
2
NOTE : 1. Pulse Test: Pulse width≤300µs, Duty Cycle≤2%.
2. Modified MOSFET symbol showing the integral reverse P-N junction diode as below.
D
TYP MAX UNIT
2
8
32
970
8.2
V
A
A
ns
µC
475
4.6
G
S
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UF840
TEST CIRCUITS AND WAVEFORMS
V
DS
MOSFET
L
VARY tp TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
p
+
V
DD
-
R
G
0V
I
AS
0.01Ω
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
BV
DSS
t
p
I
AS
V
DS
V
DD
0
t
AV
FIGURE 2. UNCLAMPED ENERGY WAVEFORMS
R
L
+
V
DD
-
DUT
R
G
V
GS
FIGURE 3. SWITCHING TIME TEST CIRCUIT
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UF840
TEST CIRCUITS AND WAVEFORMS (Cont.)
t
ON
t
DLY(ON)
t
R
V
DS
90%
t
OFF
t
DLY(OFF)
t
F
90%
MOSFET
0
10%
90%
10%
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 4. RESISTIVE SWITCHING WAVEFORMS
CURRENT
REGULATOR
V
DS
(ISOLATED
SUPPLY)
12V
BATTERY
0.2μF
SAME TYPE
AS DUT
50KΩ
0.3μF
D
DUT
G
I
G (REF)
0
I
G
CURRENT
SAMPLING
RESISTOR
S
V
DS
I
D
CURRENT
SAMPLING
RESISTOR
FIGURE 5. GATE CHARGE TEST CIRCUIT
V
DD
Q
G(TOT)
Q
GD
Q
GS
V
GS
V
DS
0
I
G(REF)
0
FIGURE 6. GATE CHARGE WAVEFORMS
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