H8/3644 Series
H8/3644
HD6473644, HD6433644
H8/3643
HD6433643
H8/3642
HD6433642
H8/3641
HD6433641
H8/3640
HD6433640
H8/3644F-ZTAT™
HD64F3644
H8/3643F-ZTAT™
HD64F3643
H8/3642AF-ZTAT™
HD64F3642A
Hardware Manual
ADE-602-087C
Rev. 4.0
08/08/98
Hitachi, Ltd.
MC-Setsu
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible
with the H8/300 CPU.
The H8/3644 Series has a system-on-a-chip architecture that includes such peripheral functions as
a D/A converter, five timers, a 14-bit PWM, a two-channel serial communication interface, and an
A/D converter. This makes it ideal for use in advanced control systems.
This manual describes the hardware of the H8/3644 Series. For details on the H8/3644 Series
instruction set, refer to the H8/300L Series Programming Manual.
Contents
Section 1
1.1
1.2
1.3
Overview
...........................................................................................................
Overview............................................................................................................................
Internal Block Diagram .....................................................................................................
Pin Arrangement and Functions ........................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1.3.2 Pin Functions........................................................................................................
1
1
5
6
6
9
Section 2
2.1
CPU
..................................................................................................................... 15
15
15
16
16
17
17
17
19
19
20
21
22
22
24
28
30
32
33
33
35
39
41
42
44
44
45
46
46
48
48
48
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2.2
2.3
2.4
2.5
2.6
2.7
Overview............................................................................................................................
2.1.1 Features ................................................................................................................
2.1.2 Address Space ......................................................................................................
2.1.3 Register Configuration .........................................................................................
Register Descriptions.........................................................................................................
2.2.1 General Registers..................................................................................................
2.2.2 Control Registers..................................................................................................
2.2.3 Initial Register Values ..........................................................................................
Data Formats......................................................................................................................
2.3.1 Data Formats in General Registers.......................................................................
2.3.2 Memory Data Formats..........................................................................................
Addressing Modes .............................................................................................................
2.4.1 Addressing Modes................................................................................................
2.4.2 Effective Address Calculation..............................................................................
Instruction Set....................................................................................................................
2.5.1 Data Transfer Instructions ....................................................................................
2.5.2 Arithmetic Operations ..........................................................................................
2.5.3 Logic Operations ..................................................................................................
2.5.4 Shift Operations....................................................................................................
2.5.5 Bit Manipulations .................................................................................................
2.5.6 Branching Instructions..........................................................................................
2.5.7 System Control Instructions .................................................................................
2.5.8 Block Data Transfer Instruction ...........................................................................
Basic Operational Timing..................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM) .........................................................
2.6.2 Access to On-Chip Peripheral Modules ...............................................................
CPU States .........................................................................................................................
2.7.1 Overview ..............................................................................................................
2.7.2 Program Execution State ......................................................................................
2.7.3 Program Halt State ...............................................................................................
2.7.4 Exception-Handling State ....................................................................................
2.8
2.9
Memory Map ..................................................................................................................... 49
Application Notes.............................................................................................................. 50
2.9.1 Notes on Data Access........................................................................................... 50
2.9.2 Notes on Bit Manipulation ................................................................................... 52
2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 58
Section 3
3.1
3.2
Exception Handling
........................................................................................ 59
59
59
59
59
61
61
61
63
72
72
73
78
79
79
80
3.3
3.4
Overview............................................................................................................................
Reset ..................................................................................................................................
3.2.1 Overview ..............................................................................................................
3.2.2 Reset Sequence.....................................................................................................
3.2.3 Interrupt Immediately after Reset ........................................................................
Interrupts............................................................................................................................
3.3.1 Overview ..............................................................................................................
3.3.2 Interrupt Control Registers ...................................................................................
3.3.3 External Interrupts................................................................................................
3.3.4 Internal Interrupts .................................................................................................
3.3.5 Interrupt Operations..............................................................................................
3.3.6 Interrupt Response Time ......................................................................................
Application Notes..............................................................................................................
3.4.1 Notes on Stack Area Use......................................................................................
3.4.2 Notes on Rewriting Port Mode Registers.............................................................
Section 4
4.1
Clock Pulse Generators
................................................................................. 83
83
83
83
84
87
88
88
4.2
4.3
4.4
4.5
Overview............................................................................................................................
4.1.1 Block Diagram......................................................................................................
4.1.2 System Clock and Subclock .................................................................................
System Clock Generator....................................................................................................
Subclock Generator ...........................................................................................................
Prescalers ...........................................................................................................................
Note on Oscillators ............................................................................................................
Section 5
5.1
5.2
Power-Down Modes
...................................................................................... 89
5.3
Overview............................................................................................................................ 89
5.1.1 System Control Registers ..................................................................................... 92
Sleep Mode........................................................................................................................ 96
5.2.1 Transition to Sleep Mode ..................................................................................... 96
5.2.2 Clearing Sleep Mode ............................................................................................ 96
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode.............................................. 96
Standby Mode.................................................................................................................... 97
5.3.1 Transition to Standby Mode ................................................................................. 97
5.3.2 Clearing Standby Mode........................................................................................ 97
5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 98
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