Dual, Precision
JFET High Speed Operational Amplifier
OP249
FEATURES
Fast slew rate: 22 V/μs typical
Settling time (0.01%): 1.2 μs maximum
Offset voltage: 300 μV maximum
High open-loop gain: 1000 V/mV minimum
Low total harmonic distortion: 0.002% typical
Improved replacement for AD712, LT1057, OP215, TL072,
and MC34082
PIN CONFIGURATIONS
OUT A
–IN A
+IN A
V–
1
2
3
4
OP249
A
B
8
7
6
5
V+
OUT B
00296-001
00296-002
–IN B
+IN B
Figure 1. 8-Lead CERDIP (Q-8) and
8-Lead PDIP (N-8)
+IN A
1
2
3
4
8
–IN A
OUT A
V+
OUT B
APPLICATIONS
Output amplifier for fast DACs
Signal processing
Instrumentation amplifiers
Fast sample-and-holds
Active filters
Low distortion audio amplifiers
Input buffer for ADCs
Servo controllers
V–
+IN B
–IN B
A
7
6
5
OP249
B
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar to
the popular single op amp, the OP42. The OP249 outperforms
available dual amplifiers by providing superior speed with
excellent dc performance. Ultrahigh open-loop gain (1 kV/mV
minimum), low offset voltage, and superb gain linearity makes
the OP249 the industry’s first true precision, dual high speed
amplifier.
With a slew rate of 22 V/μs typical and a fast settling time of less
than 1.2 μs maximum to 0.01%, the OP249 is an ideal choice for
high speed bipolar DAC and ADC applications. The excellent
dc performance of the OP249 allows the full accuracy of high
resolution CMOS DACs to be realized.
0.01
Symmetrical slew rate, even when driving large load, such as,
600 Ω or 200 pF of capacitance and ultralow distortion, make
the OP249 ideal for professional audio applications, active filters,
high speed integrators, servo systems, and buffer amplifiers.
The OP249 provides significant performance upgrades to the
TL072, AD712, OP215, MC34082, and LT1057.
870ns
100
90
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 10kΩ
A
V
= 1
100
90
00296-003
00296-004
10mV
500ns
0.001
20
5V
1µs
100
1k
10k 20k
Figure 3. Fast Settling (0.01%)
Figure 4. Low Distortion, A
V
= 1, R
L
= 10 kΩ
Figure 5. Excellent Output Drive, R
L
= 600 Ω
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
00296-005
10
0%
10
0%
OP249
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 13
Open-Loop Gain Linearity ....................................................... 14
Offset Voltage Adjustment ........................................................ 14
Settling Time............................................................................... 14
DAC Output Amplifier.............................................................. 15
Disscusion on Driving ADCs ................................................... 16
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/07—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3 and Table 4....................................................... 5
Changes to Table 5............................................................................ 6
Changes to Figure 31...................................................................... 11
Changes to Figure 37 and Figure 38............................................. 12
Deleted OP249 SPICE Macro-Model Section ............................ 14
Deleted Figure 18; Renumbered Sequentially ............................ 14
Deleted Table I ................................................................................ 15
Changes to Discussion on Driving ADCs Section..................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
9/01—Rev. D to Rev. E
Edits to Features and Pin Connections ..........................................1
Edits to Electrical Characteristics .............................................. 2, 3
Edits to Absolute Maximum Ratings, Package Type, and
Ordering Guide..................................................................................4
Deleted Wafer Test Limits and Dice Characteristics Section ......5
Edits to Typical Performance Characteristics................................8
Edits to Macro-Model Figure........................................................ 15
Edits to Outline Dimensions......................................................... 17
Rev. F | Page 2 of 20
OP249
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
S
= ±15 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
Offset Voltage
Long Term Offset Voltage
1
Offset Stability
Input Bias Current
Input Offset Current
Input Voltage Range
2
Symbol
V
OS
V
OS
I
B
I
OS
IVR
Conditions
Min
OP249A
Typ
0.2
1.5
30
6
12.5
±11
Common-Mode Rejection
Power-Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
A
VO
V
O
V
CM
= ±11 V
V
S
= ± 4.5 V to ±18 V
V
O
= ±10 V, R
L
= 2 kΩ
R
L
= 2 kΩ
80
1000
±12.0
Short-Circuit Current Limit
I
SC
Output shorted to
ground
±20
Supply Current
Slew Rate
Gain Bandwidth Product
3
Settling Time
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
Voltage Noise Density
I
SY
SR
GBW
t
S
Θ
M
Z
IN
R
O
e
n
p-p
e
n
No load, V
O
= 0 V
R
L
= 2 kΩ, C
L
= 50 pF
10 V step 0.01%
4
0 dB gain
−33
5.6
22
4.7
0.9
55
10
12
||6
35
2
75
26
17
16
0.003
±15
−12.5
36
±50
7.0
18
3.5
1.2
±20
–33
5.6
22
4.7
0.9
55
10
12
||6
35
2
75
26
17
16
0.003
±15
−12.5
90
12
1400
12.5
Max
0.5
0.8
75
25
±11
80
31.6
500
±12.0
–12.5
36
±50
7.0
–12.5
90
12
1200
12.5
Min
OP249F
Typ
0.2
1.5
30
6
12.5
Max
0.7
1.0
75
25
Unit
mV
mV
μV/month
pA
pA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
mA
mA
mA
V/μs
MHz
μs
Degrees
Ω||pF
Ω
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
V
CM
= 0 V, T
A
= 25°C
V
CM
= 0 V, T
A
= 25°C
50
18
3.5
1.2
Current Noise Density
Voltage Supply Range
1
2
i
n
V
S
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
f
O
= 10 kHz
f
O
= 1 kHz
±4.5
±18
±4.5
±18
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent wafer lots at 125°C with LTPD of three.
Guaranteed by CMR test.
3
Guaranteed by design.
4
Settling time is sample tested.
Rev. F | Page 3 of 20
OP249
V
S
= ±15 V, T
A
= 25°C, unless otherwise noted.
Table 2.
Parameter
Offset Voltage
Input Bias Current
Input Offset Current
Input Voltage Range
1
Symbol
V
OS
I
B
I
OS
IVR
Conditions
V
CM
= 0 V, T
A
= 25°C
V
CM
= 0 V T
A
= 25°C
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
A
VO
V
O
V
CM
= ±11 V
V
S
= ±4.5 V to ±18 V
V
O
= ±10 V; R
L
= 2 kΩ
R
L
= 2 kΩ
76
500
±12.0
Short-Circuit Current Limit
I
SC
Output shorted to ground
±20
Supply Current
Slew Rate
Gain Bandwidth Product
2
Settling Time
Phase Margin
Differential Input Impedance
Open-Loop Output Resistance
Voltage Noise
Voltage Noise Density
I
SY
SR
GBW
t
S
Θ
M
Z
IN
R
O
e
n
p-p
e
n
No load; V
O
= 0 V
R
L
= 2 kΩ, C
L
= 50 pF
10 V step 0.01%
0 dB gain
−33
5.6
22
4.7
0.9
55
10
12
||6
35
2
75
26
17
16
0.003
±15
−12.5
36
±50
7.0
−12.0
90
12
1100
12.5
Min
OP249G
Typ
0.4
40
10
12.5
Max
2.0
75
25
Unit
mV
pA
pA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
mA
mA
mA
V/μs
MHz
μs
Degree
Ω||pF
Ω
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V
50
18
1.2
Current Noise Density
Voltage Supply Range
1
2
i
n
V
S
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 100 Hz
f
O
= 1 kHz
f
O
= 10 kHz
f
O
= 1 kHz
±4.5
±18
Guaranteed by CMR test.
Guaranteed by design.
Rev. F | Page 4 of 20
OP249
V
S
= ±15 V, −40°C ≤ T
A
≤ +85°C for F grade and −55°C ≤ T
A
≤ +125°C for A grade, unless otherwise noted.
Table 3.
Parameter
Offset Voltage
Offset Voltage Temperature Coefficient
Input Bias Current
1
Input Offset Current
1
Input Voltage Range
2
Symbol
V
OS
TCV
OS
I
B
I
OS
IVR
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
A
VO
V
O
V
CM
= ±11 V
V
S
= ±4.5 V to ±18 V
R
L
= 2 kΩ; V
O
= ±10 V
R
L
= 2 kΩ
76
500
±12
Supply Current
1
2
Conditions
Min
OP249A
Typ
Max
0.12
1.0
1
4
0.04
12.5
−12.5
110
5
1400
12.5
−12.5
5.6
5
20
4
Min
OP249F
Typ
Max
0.5
1.1
2.2
0.3
0.02
12.5
6
4.0
1.2
Unit
mV
μV/°C
nA
nA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
±11
80
50
250
±12
7.0
−12.5
5.6
7.0
−12.5
90
7
1200
12.5
100
I
SY
No load, V
O
= 0 V
T
A
= 85°C for F grade; T
A
= 125°C for A grade.
Guaranteed by CMR test.
V
S
= ±15 V, −40°C ≤ T
A
≤ +85°C, unless otherwise noted.
Table 4.
Parameter
Offset Voltage
Offset Voltage Temperature Coefficient
Input Bias Current
1
Input Offset Current
1
Input Voltage Range
2
Symbol
V
OS
TCV
OS
I
B
I
OS
IVR
Conditions
Min
OP249G
Typ
1.0
6
0.5
0.04
12.5
−12.5
95
10
1200
12.5
−12.5
5.6
Max
3.6
25
4.5
1.5
Unit
mV
μV/°C
nA
nA
V
V
V
dB
μV/V
V/mV
V
V
V
mA
±11
Common-Mode Rejection
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing
CMR
PSRR
A
VO
V
O
V
CM
= ±11 V
V
S
= ±4.5 V to ±18 V
R
L
= 2 kΩ; V
O
= ±10 V
R
L
= 2 kΩ
76
250
±12.0
Supply Current
1
2
100
I
SY
No load, V
O
= 0 V
7.0
T
A
= 85°C.
Guaranteed by CMR test.
Rev. F | Page 5 of 20
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
