A4983
DMOS Microstepping Driver with Translator
Features and Benefits
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Low R
DS(ON)
outputs
Automatic current decay mode detection/selection
Mixed and Slow current decay modes
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Very thin profile QFN package
Thermal shutdown circuitry
Description
The A4983 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors in full-, half-, quarter-, eighth-, and
sixteenth-step modes, with an output drive capacity of up to
35 V and ±2 A. The A4983 includes a fixed off-time current
regulator which has the ability to operate in Slow or Mixed
decay modes.
The translator is the key to the easy implementation of the
A4983. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A4983 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
The chopping control in the A4983 automatically selects the
current decay mode (Slow or Mixed). When a signal occurs at
the STEP input pin, the A4983 determines if that step results
in a higher or lower current in each of the motor phases. If
the change is to a higher current, then the decay mode is set
to Slow decay. If the change is to a lower current, then the
current decay is set to Mixed (set initially to a fast decay for
a period amounting to 31.25% of the fixed off-time, then to a
Continued on the next page…
Package: 28-pin QFN (suffix ET)
Approximate size
Typical Application Diagram
V
DD
0.22
μ
F
VREG
VDD
Microcontroller or
Controller Logic
MS1
MS2
MS3
SLEEP
STEP
DIR
RESET
ENABLE
REF
ROSC
VCP CP1
0.1
μ
F
CP2
0.1
μF
V
BB
VBB
VBB
OUT1A
OUT1B
RS1
A4983
OUT2A
OUT2B
RS2
4983DS, Rev. 1
A4983
DMOS Microstepping Driver with Translator
lockout (UVLO), and crossover-current protection. Special power-
on sequencing is not required.
The A4983 is supplied in a 5 mm × 5 mm × 0.90 nominal surface
mount QFN package with exposed thermal pad (suffix ET). The
package is lead (Pb) free (suffix –T), with 100% matte tin plated
leadframe.
Description (continued)
slow decay for the remainder of the off-time). This current decay
control scheme results in reduced audible motor noise, increased
step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided to
improve power dissipation during PWM operation. Internal circuit
protection includes: thermal shutdown with hysteresis, undervoltage
Selection Guide
Part Number
A4983SETTR-T
Pb-free
Yes
Package
28-pin QFN with exposed thermal pad
Packing
1500 pieces per 7-in. reel
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Output Current
Logic Input Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
Symbol
V
BB
I
OUT
V
IN
V
SENSE
V
REF
T
A
T
J
(max)
T
stg
Range S
Duty Cycle < 20%
Notes
Rating
35
±2
±2.5
–0.3 to 7
0.5
4
–20 to 85
150
–55 to 150
Units
V
A
A
V
V
V
ºC
ºC
ºC
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A4983
DMOS Microstepping Driver with Translator
Functional Block Diagram
0.22 F
VREG
ROSC
CP1
0.1 F
CP2
VDD
Current
Regulator
OSC
Charge
Pump
VCP
0.1 F
DMOS Full Bridge
VBB1
REF
DAC
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
Gate
Drive
Control
Logic
DMOS Full Bridge
SENSE1
STEP
DIR
RESET
MS1
MS2
Translator
VBB2
R
S1
OUT2A
OUT2B
MS3
ENABLE
SLEEP
DAC
R
S2
PWM Latch
Blanking
Mixed Decay
SENSE2
V
REF
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A4983
DMOS Microstepping Driver with Translator
ELECTRICAL CHARACTERISTICS
1
at T
A
= 25°C, V
BB
= 35 V (unless otherwise noted)
Characteristics
Output Drivers
Load Supply Voltage Range
Logic Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
Symbol
Test Conditions
Operating
During Sleep Mode
Operating
Source Driver, I
OUT
= –1.5 A
Sink Driver, I
OUT
= 1.5 A
Source Diode, I
F
= –1.5 A
Sink Diode, I
F
= 1.5 A
f
PWM
< 50 kHz
Operating, outputs disabled
Sleep Mode
f
PWM
< 50 kHz
Outputs off
Sleep Mode
Min.
8
0
3.0
–
–
–
–
–
–
–
–
–
–
V
DD
0.7
V
IN
= V
DD
0.7
–
–20
–20
–
–
150
0.7
20
23
0
–3
–
–
–
100
–
–
2.35
0.05
Typ.
2
–
–
–
0.350
0.300
–
–
–
–
–
–
–
–
–
–
<1.0
<1.0
100
100
300
1
30
30
–
0
–
–
–
475
165
15
2.7
0.10
Max.
35
35
5.5
0.450
0.370
1.2
1.2
4
2
10
8
5
10
–
V
DD
0.3
20
20
–
–
500
1.3
40
37
4
3
±15
±5
±5
800
–
–
3
–
Units
V
V
V
Ω
Ω
V
V
mA
mA
μA
mA
mA
μA
V
V
μA
μA
kΩ
kΩ
mV
μs
μs
μs
V
μA
%
%
%
ns
°C
°C
V
V
V
BB
V
DD
R
DSON
V
F
I
BB
Motor Supply Current
Logic Supply Current
Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select 2
Microstep Select 3
Input Hysteresis
Blank Time
Fixed Off-Time
Reference Input Voltage Range
Reference Input Current
Current Trip-Level Error
3
Crossover Dead Time
Protection
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
UVLO Enable Threshold
UVLO Hysteresis
I
DD
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
R
MS2
R
MS3
V
HYS(IN)
t
BLANK
t
OFF
V
REF
I
REF
err
I
V
IN
= V
DD
0.3
OSC > 3 V
R
OSC
= 25 kΩ
V
REF
= 2 V,
%I
TripMAX
=
38.27%
V
REF
= 2 V,
%I
TripMAX
= 70.71%
V
REF
= 2 V,
%I
TripMAX
= 100.00%
t
DT
T
J
T
JHYS
UV
LO
UV
HYS
V
DD
rising
1
Negative current is defined as coming out of (sourcing from) the specified device pin.
2
Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
3
err
individual units, within the specified maximum and minimum limits.
I
= (I
Trip
– I
Prog
)
⁄
I
Prog
, where I
Prog
= %I
TripMAX
I
TripMAX
.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A4983
DMOS Microstepping Driver with Translator
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
Package ET; 4-layer PCB, based on JEDEC standard
Value Units
32
ºC/W
*In still air. Additional thermal information available on Allegro Web site.
Maximum Power Dissipation, P
D
(max)
5.5
5.0
4.5
4.0
Power Dissipation, P
D
(W)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
(R
θ
J
A
=
32
ºC
/W
)
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
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