CY24260
Clock Generator for PDA/MP3/LCD
Features
Supports PDA and Web-Pad clocking requirements
Audio Clock for hardware codec or for AC 97 codec
LCD controller programmable clock
Advanced power management with synchronous clock
throttling
• Power-down I
PD
< 200µA
• Independent phase-locked loop (PLL)-disable
capability
• Space-saving 20-lead TSSOP package
•
•
•
•
Table 1. Frequency Table
S(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
LCDS1
0
0
1
1
LCDS0
0
1
0
1
Faudio (MHz)
Clock Off, PLL Off
24.576
20
N/A
9.216
16.25
22.5792
29.49
2.048
2.8224
4.096
5.6448
6.144
8.192
11.2896
12.288
FLCD (MHz)
Clock Off, PLL Off
48
24
40
Block Diagram
Faudio_OE
S(0:3)
PLL1
Faudio
Pin Configuration
[1]
Xin
VDD
*S3
VSS
REFout
*Faudio_OE
PLL2
FLCD
PD#
LCDS(0:1)
*PD#
**LCDS0
**LCDS1
VSS
XIN
XOUT
OSCILLATOR
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Xout
S2*
S1*
S0*
VDD
Faudio
VSS
REFen*
FLCD
VDD
REFout
20 pin TSSOP
REFen
Note:
1. * = Pull-up; ** = pull-down.
Cypress Semiconductor Corporation
Document #: 38-07375 Rev. **
•
3901 North First Street
•
San Jose
CY24260
•
CA 95134 • 408-943-2600
Revised February 22, 2002
CY24260
Pin Description
Pin
2,11,16
4,10,14
17,18,19,3
8,9
7
5
13
15
6
12
20
1
Name
VDD
VSS
S(0:3)
LCDS(0:1)
PD#
REFout
REFen
Faudio
Faudio_OE
FLCD
Xout
Xin
I
PU
I
PD
I
PU
O
I
PU
O
I
PU
O
O
I
PWR
I/O
Connect to 3.3V or 5V
Power ground
Faudio frequency select lines
FLCD Frequency select lines. Use a 10KW pull-up.
Power-down Control.
0 = device check down, 1= running. All outputs
are turned off immediately upon PD# assertion.
Buffered output of X
IN
REF Output Control.
0 = Disable REFout, 1 = Enable REFout.
Buffered output of PLL1
Faudio Output Control.
1= Faudio is running, 0 = Faudio is stopped.
Faudio is stopped synchronously such that there are no glitches or short
pulses.
Buffered output of PLL2
Oscillator Buffer Output.
Connect to crystal. Do not connect when an
external clock is applied at X
IN
. No internal capacitor.
Oscillator Buffer Input.
Connect to a crystal or to an external clock. No
internal capacitor.
Description
Document #: 38-07375 Rev. **
Page 2 of 5
CY24260
Maximum Ratings
Input Voltage Relative to V
SS
:.............................. V
SS
– 0.3V
Input Voltage Relative to V
DDQ
or AV
DD
: ............. V
DD
+ 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature: .................................... 0°C to +70°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= 3.3V + 5%, T
A
= 0°C to +70°C
Parameter
V
IH
V
IL
I
IN
V
OL
V
OH
I
DD
I
DD
I
DDPD
C
IN
Description
Input HIGH Voltage
Input LOW Voltage
Input Current
Output LOW Voltage
Output HIGH Voltage
Operating Supply Current
Operating Supply Current
Power-down Supply Current
Input Pin Capacitance
V
IN
= 0V or V
IN
= V
DDQ
I
OL
= 8 mA
I
OH
= –8 mA
15 pF Load, FLCD PLL Off
15 pF Load, FLCD PLL On
15 pF Load
2.4
7.7
15
50
4
10
20
100
–10
Conditions
Min.
2.0
0.8
10
0.4
Typ.
Max.
Unit
V
V
µA
V
V
mA
mA
µA
pF
AC Parameters
V
DD
= 3.3V + 5%, T
A
= 0°C to +70°C
Parameter
X
IN
REF
OUT
T
R
T
F
T
DC
T
CCJ
T
STABLE
Description
Input Crystal or Clock Frequency
REFout Frequency
Output Rise Time: Faudio, FLCD
Output Fall Time: Faudio, FLCD
Output Duty Cycle
Cycle-to-Cycle Jitter
Stabilization Time
1.5V
0.2 V
DD
to 0.8 V
DD
0.8 V
DD
to 0.2 V
DD
1.5V
1.5
1.5
45
Conditions
Min.
Typ.
3.6864
3.6864
2
2
50
±100
3
3
55
±250
3
Max.
Unit
MHz
MHz
ns
ns
%
ps
ms
Faudio_OE
Faudio
Figure 1. Faudio Enable/Disable Timing
Clock
Faudio, REFout, FLCD
Max Load
15
Units
pF
Ordering Information
Part Number
CY24260ZC
CY24260ZCT
Package Type
20-pin TSSOP
20-pin TSSOP – Tape and Reel
Product Flow
Commercial, 0°–70° C
Commercial, 0°–70° C
Document #: 38-07375 Rev. **
Page 3 of 5
CY24260
Package Drawing and Dimensions
20-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z20
51-85118
All product and company names mentioned in this document may be the trademarks of their repsective holders.
Document #: 38-07375 Rev. **
Page 4 of 5
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY24260
Document Title: CY24260 Clock Generator for PDA/MP3/LCD
Document Number: 38-07375
REV.
**
ECN NO.
112832
Issue Date
03/04/02
Orig. of Change
DMG
Description of Change
New Data Sheet
Document #: 38-07375 Rev. **
Page 5 of 5
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