March 2001
®
AS4C4M4EOQ
AS4C4M4E1Q
4M
✕
4 CMOS QuadCAS DRAM (EDO) family
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 495 mW max
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
• Refresh
- 4096 refresh cycles, 64 ms refresh interval for
4C4M4EOQ
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4E1Q
- RAS-only and hidden refresh or CAS-before-RAS refresh
or self-refresh
• TTL-compatible
• 4 separate CAS pins allow for separate I/O operation
• JEDEC standard package
- 300 mil, 28-pin SOJ
- 300 mil, 28-pin TSOP
• 5V power supply
• Latch-up current
≥
200 mA
• ESD protection
≥
2000 mV
Pin arrangement
SOJ
V
CC
I/O0
I/O1
WE
RAS
*NC/A11
CAS0
CAS1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O3
I/O2
CAS3
OE
A9
CAS2
NC
A8
A7
A6
A5
A4
GND
V
CC
I/O0
I/O1
WE
RAS
*NC/A11
CAS0
CAS1
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
Pin designation
TSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
I/O3
I/O2
CAS3
OE
A9
CAS2
NC
A8
A7
A6
A5
A4
GND
Pin(s)
A0 to A11
RAS
CAS
WE
I/O0 to I/O3
OE
V
CC
GND
NC
Description
Address inputs
Row address strobe
Column address strobe
Write enable
Input/output
Output enable
Power
Ground
No Connection
AS4C4M4E0
11
12
13
14
* NC on 2K refresh version; A11 on 4K refresh version
Selection guide
Symbol
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
Maximum CMOS standby current
3/22/01; v.1.0
AS4C4M4E0
4C4M4EOQ/E1Q-50
50
25
12
13
85
20
110
1.0
4C4M4EOQ/E1-60
60
30
15
15
100
24
100
1.0
Unit
ns
ns
ns
ns
ns
ns
mA
mA
P. 1 of 16
t
RAC
t
CAA
t
CAC
t
OEA
t
RC
t
PC
I
CC1
I
CC5
Alliance Semiconductor
Copyright © Alliance Semiconductor. All rights reserved.
AS4C4M4EOQ
AS4C4M4E1Q
®
Functional description
The 4C4M4EOQ, and AS4C4M4E1Q are high performance 16-megabit CMOS Quad CAS Dynamic Random Access Memories (DRAM)
organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques
resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family
is optimized for use as main memory in PC, workstation, router and switch applications.
These products feature a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Extended data out (EDO) read mode enables 50 MHz operation using 50 ns devices. Four individual CAS pins allow for separate I/O
operation which enables the device to operate in parity mode. In contrast to 'fast page mode' devices, data remains active on outputs after
CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus
contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS
going high.
Refresh on the 4096 address combinations of A0 to A11 must be performed every 64 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 4096 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
• CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
• Self-refresh cycles
The 4C4M4EOQ and AS4C4M4E1Q are available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The 4C4M4EOQ and
AS4C4M4E1Q operate with a single power supply of 5V ± 0.5V. All provide TTL compatible inputs and outputs.
3/22/01; v.1.0
Alliance Semiconductor
P. 2 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
Logic block diagram for 4K refresh
V
CC
GND
Refresh
controller
Column decoder
Sense amp
Data
I/O
buffers
I/O0 to I/O3
RAS
RAS clock
generator
CAS
CAS clock
generator
WE
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
OE
Address buffers
Row decoder
4,194,304 × 4
Array
(16,777,216)
Logic block diagram for 2K refresh
V
CC
GND
Refresh
controller
Column decoder
Sense amp
Data
I/O
buffers
I/O0 to I/O3
RAS
RAS clock
generator
CAS
CAS clock
generator
WE
WE clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
OE
Address buffers
Row decoder
4,194,304 × 4
Array
(16,777,216)
Substrate bias
generator
Recommended operating conditions
Parameter
Supply voltage
4C4M4EOQ
AS4C4M4E1Q
4C4M4EOQ
AS4C4M4E1Q
Symbol
V
CC
GND
Input voltage
Ambient operating temperature
†
Min
4.5
0.0
2.4
–0.5
†
0
Nominal
5.0
0.0
–
–
Max
5.5
0.0
V
CC
0.8
70
Unit
V
V
V
V
°C
V
IH
V
IL
T
A
V
IL
min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
3/22/01; v.1.0
Alliance Semiconductor
P. 3 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
Absolute maximum ratings
Parameter
Input voltage
Input voltage (DQs)
Power supply voltage
Storage temperature (plastic)
Soldering temperature × time
Power dissipation
Short circuit output current
Symbol
V
in
V
DQ
V
CC
T
STG
T
SOLDER
P
D
I
out
Min
-1.0
-1.0
-1.0
-55
–
–
–
Max
+7.0
V
CC
+ 0.5
+7.0
+150
260 × 10
1
50
Unit
V
V
V
°C
o
C × sec
W
mA
DC electrical characteristics (AS4C4M4E0/E1)
-50
Parameter
Symbol Test conditions
0V
≤
V
in
≤
+5.5V,
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
+5.5V
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
RAS = UCAS = LCAS
≥
V
IH
RAS cycling, UCAS = LCAS
≥
V
IH
,
t
RC
= min of RAS low after XCAS
low.
RAS = V
IL
, UCAS or LCAS,
address cycling: t
HPC
= min
RAS = UCAS = LCAS = V
CC
- 0.2V
I
OUT
= -5.0 mA
I
OUT
= 4.2 mA
RAS, UCAS or LCAS cycling, t
RC
=
min
RAS = UCAS = LCAS
≤
0.2V,
WE = OE
≥
V
CC
- 0.2V,
all other inputs at 0.2V or
V
CC
- 0.2V
Min
-5
-5
–
–
Max
+5
+5
110
2.0
Min
-5
-5
–
–
-60
Max
+5
+5
100
2.0
Unit
µA
µA
mA
mA
1,2
Notes
Input leakage current I
IL
Output leakage current I
OL
Operating power
supply current
TTL standby power
supply current
I
CC1
I
CC2
Average power supply
current, RAS refresh I
CC3
mode or CBR
EDO page mode
average power supply I
CC4
current
CMOS standby power
I
CC5
supply current
Output voltage
V
OH
V
OL
–
110
–
100
mA
1
–
90
–
80
mA
1, 2
–
2.4
–
–
1.0
–
0.4
110
–
2.4
–
–
1.0
–
0.4
100
mA
V
V
mA
CAS before RAS refresh
I
CC6
current
Self refresh current
I
CC7
–
0.6
–
0.6
mA
3/22/01; v.1.0
Alliance Semiconductor
P. 4 of 16
AS4C4M4EOQ
AS4C4M4E1Q
®
DC electrical characteristics (AS4LC4M4E0/E1)
-50
Parameter
Input leakag
e c
urrent
Symbol Test conditions
I
IL
0V
≤
V
in
≤
V
CC
(max)
Pins not under test = 0V
D
OUT
disabled, 0V
≤
V
out
≤
V
CC
(max)
RAS, UCAS, LCAS, Address cycling;
t
RC
=min
RAS = UCAS = LCAS
≥
V
IH
,
all other inputs at V
IH
or V
IL
RAS cycling, UCAS = LCAS
≥
V
IH
,
t
RC
= min of RAS low after XCAS low.
RAS = V
IL
, UCAS or LCAS,
address cycling: t
HPC
= min
RAS = UCAS = LCAS = V
CC
- 0.2V,
F=0
I
OUT
= -2.0 mA
I
OUT
= 2 mA
RAS, UCAS or LCAS cycling, t
RC
=
min
RAS = UCAS = LCAS
≤
0.2V,
WE = OE = V
CC
- 0.2V,
all other inputs at 0.2V or V
CC
-
0.2V
Min
-5
-5
–
–
Max
+5
+5
85
2.0
Min
-5
-5
–
–
-60
Max
+5
+5
75
2.0
Unit
µ
A
µ
A
Notes
Output leakage current I
OL
Operating power
supply current
TTL standby power
supply current
Average power supply
current, RAS refresh
mode or CBR
EDO page mode
average power supply
current
CMOS standby power
supply current
Output voltage
I
CC1
I
CC2
I
CC3
mA
mA
4,5
–
80
–
70
mA
4
I
CC4
I
CC5
V
OH
V
OL
–
85
–
75
mA
4, 5
–
2.4
–
–
200
–
0.4
80
–
2.4
–
–
200
–
0.4
70
µA
V
V
mA
CAS before RAS refresh
I
CC6
current
Self refresh current
I
CC7
–
0.3
–
0.3
mA
3/22/01; v.1.0
Alliance Semiconductor
P. 5 of 16
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