Data Sheet
PT7A6632 32-Channel HDLC Controller
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Features
• Provides up to 32 full-duplex HDLC/SDLC
channels
• Compatible with 1.544 Mb/s T1 and 2.048Mb/s
CEPT PCM-30 carrier format
• Provides on-board buffer memory management
• Supports standard hyperchannel configuration and
fully programmable hyperchannel configuration
• Provides on-board CRC-16, automatic flag and
zero insertion and deletion functions in HDLC
format
• Provides programmable tri-state outputs to T1/E1
serial interface and FILL/MASK, thus enabling up
to 8 devices connecting to a TDM bus
• Provides data rate adaptation functions
• Compatible with HDLC, SNA SDLC, X.25, X.75,
LAPB, and LAPD protocols
• Support non-HDLC signaling channels
• Single +5V power supply
• Package: 68-pin PLCC
Figure 1. Application Diagram of PT7A6632
Applications
• Primary rate interfaces
• Basic-rate D-channel controller
• Multi-channel HDLC interfaces
Introduction
The PT7A6632 HDLC controller operates at layer 2
(data link protocol level) of the Open Systems Inter-
connection (OSI) reference model. It supports HDLC
and ISDN implementations.
The PT7A6632 processes data transmitting and re-
ceiving on a T1 or E1 communication link. It con-
nects between the T1/E1 serial bus and an external
memory shared with CPU(s), multiplexing /
demultiplexing up to 32 fully-duplex high-speed data
channels.
It provides additional functions that support X.30 and
X.31 rate adaptation and fully flexible hyperchannels.
D0-D7
CPU
External
Shared
Memory
A0-A15
HDLC
PT7A6632
E1/T1
Trunk
Interface
T1/CEPT
PCM-30
Line
PT019(05/02)
1
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Contents
Features ....................................................................................................................................................... 1
Applications ................................................................................................................................................ 1
Introduction ................................................................................................................................................. 1
Block Diagram ............................................................................................................................................ 4
Pin Information ........................................................................................................................................... 4
Pin Assignment .................................................................................................................................. 4
Pin Configuration .............................................................................................................................. 5
Pin Description .................................................................................................................................. 6
Functional Description ................................................................................................................................ 9
General Description ........................................................................................................................... 9
Transmit Bit-Level Processor ........................................................................................................... 10
Timing .................................................................................................................................... 10
Data Rate Adaptation ............................................................................................................. 10
Hyperchannel ......................................................................................................................... 13
Tri-State Serial Data Output TSER ........................................................................................ 14
Channel Operation Modes...................................................................................................... 14
Data Transmission Order ........................................................................................................ 14
Receive Bit-Level Processor ............................................................................................................ 15
Timing .................................................................................................................................... 15
Data Rate Adaptation ............................................................................................................. 15
HDLC Frame Validity ............................................................................................................ 15
Hyperchannel ......................................................................................................................... 15
Channel Operation Modes...................................................................................................... 15
Data Reception Order............................................................................................................. 18
Memory Manager ............................................................................................................................ 18
State / Control Machine ................................................................................................................... 19
PT019(05/02)
2
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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External Memory Organization and Definition ......................................................................................... 20
General Structure ............................................................................................................................. 20
Activation Memory .......................................................................................................................... 21
Channel Activation Byte ........................................................................................................ 21
Channel Buffer Pointers ......................................................................................................... 21
Data Processing Memory ................................................................................................................. 24
General ................................................................................................................................... 24
Transmit Data Buffer .............................................................................................................. 24
Transmit Command Buffer ..................................................................................................... 26
Minimum Number of Data Bytes in a Tx Buffer.................................................................... 30
Receive Data Buffer ............................................................................................................... 31
Receive Command Buffer ...................................................................................................... 33
Minimum Buffer Size ............................................................................................................. 37
Device Operation ...................................................................................................................................... 38
Device Initialization ......................................................................................................................... 38
Channel Initialization ....................................................................................................................... 38
Data Transmission and Reception Operation ................................................................................... 39
Channel Period ................................................................................................................................ 41
Memory Address ............................................................................................................................. 42
Memory Address Extension ................................................................................................... 42
Activation Memory Address................................................................................................... 42
Memory Address Restrictions................................................................................................. 43
Interrupt Indication .......................................................................................................................... 43
Detailed Specifications .............................................................................................................................. 48
Absolute Maximum Ratings ............................................................................................................ 48
Recommended Operating Conditions .............................................................................................. 48
DC Electrical, Power Supply and Capacitance Characteristics ........................................................ 49
AC Characteristics ........................................................................................................................... 50
Serial Interface........................................................................................................................ 50
External Memory Interface ..................................................................................................... 54
Channel Activation/Deactivation ............................................................................................ 56
Input Characteristics ............................................................................................................... 57
Output Characteristics ............................................................................................................ 58
Mechanical Specifications ............................................................................................................... 59
Ordering Information ................................................................................................................................ 60
Notes ......................................................................................................................................................... 61
PT019(05/02)
3
Ver:2
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Block Diagram
Figure 2. Block Diagram of PT7A6632
16
A0-A15
D0-D7
READ
WRITE
AS
DMND
ATTN
ATACK
SYSACC
INTR
8
RSER
Receive
Bit-Level
Processor
Memory
Manager
RSYNC
RRED
RCLK
TCLK
TSER
TMAX
TSEREN
SYSCLK
5
CH0-CH4
Transmit
Bit-Level
Processor
State / Control Machine
Rx/Tx
2
RESET UAEN MDFS HCS0-HCS1 T1/CEPT SIS
Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p
Memory Interface
Serial Interface
CPU Interface
State & Control
Power
PT019(05/02)
Sym b ol
D0-D7, A0-A15, READ, WRITE, AS,
DMND
RSER, RSYNC, RRED, TSER, TMAX,
SYSCLK, TCLK, RCLK, TSEREN
ATTN, ATACK, SYSACC, INTR
SIS, T1/CEPT, HCS0, HCS1, MDFS,
UAEN, RESET, CH0-CH4, Rx/Tx
V
CC
, GND
F u n ct ion
Data, Addresses & Signals with Shared
Memory
Data & Timing with Serial Interface
Signals with CPU
Device Status & Control Signals
Power & Ground
Ver:2
4
Data Sheet
PT7A6632 32-Channel HDLC Controller
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Pin Configuration
Figure 3. Pin Configuration
CH1
CH2
CH3
CH4
Rx/Tx
TCLK
SYSCLK
TSER
V
CC
GND
GND
D0
D1
D2
D3
D4
D5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
NC
CH0
HCS1
HCS0
T1/CEPT
RESET
SIS
TMAX
NC
TSEREN
RCLK
RSYNC
RRED
RSER
NC
GND
GND
68-Pin
PLCC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC
INTR
AS
ATTN
SYSACC
GND
GND
GND
V
CC
WRITE
READ
ATACK
DMND
MDFS
UAEN
A15
A14
PT019(05/02)
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NC
Top View
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
5
Ver:2
FPGA/CPLD
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