A3930
and
A3931
Automotive 3-Phase BLDC Controller and MOSFET Driver
Features and Benefits
▪
▪
▪
▪
▪
▪
▪
▪
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High current 3-phase gate drive for N-channel MOSFETs
Synchronous rectification
Cross-conduction protection
Charge pump and top-off charge pump for 100% PWM
Integrated commutation decoder logic
Operation over 5.5 to 50 V supply voltage range
Extensive diagnostics output
Provides +5 V Hall sensor power
Low-current sleep mode
Description
The A3930 and A3931 are 3-phase brushless dc (BLDC) motor
controllers for use with N-channel external power MOSFETs.
They incorporate much of the circuitry required to design a
cost effective three-phase motor drive system, and have been
specifically designed for automotive applications.
A key automotive requirement is functionality over a wide
input supply range. A unique charge pump regulator provides
adequate (>10 V) gate drive for battery voltages down to 7 V,
and allows the device to operate with a reduced gate drive at
battery voltages down to 5.5 V. Power dissipation in the charge
pump is minimized by switching from a voltage doubling mode
at low supply voltage to a dropout mode at the nominal running
voltage of 14 V.
A bootstrap capacitor is used to provide the above-battery
supply voltage required for N-channel MOSFETs. An internal
charge pump for the high-side drive allows for dc (100% duty
cycle) operation.
Internal fixed-frequency PWM current control circuitry can
be used to regulate the maximum load current. The peak
load current limit is set by the selection of an input reference
voltage and external sensing resistor. The PWM frequency is
set by a user-selected external RC timing network. For added
flexibility, the PWM input can be used to provide speed and
Continued on the next page…
Package: 48 Lead LQFP with exposed
thermal pad (suffix JP)
Typical Application
3930-DS
Preliminary Data Sheet
Subject to Change Without Notice
April 6, 2006
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
combination on the Hall inputs. In this state, the A3930 indicates
a logic fault, but the A3931 prepositions the motor in an unstable
starting position suitable for start-up algorithms in microprocessor-
driven “sensor-less” control systems.
Both devices are supplied in a 48-pin LQFP with exposed thermal
pad. This is a small footprint (81 mm
2
) power package, that is lead
(Pb) free, with 100% matte tin leadframe plating.
Description (continued)
torque control, allowing the internal current control circuit to set
the maximum current limit.
Efficiency is enhanced by using synchronous rectification. The
power FETs are protected from shoot-through by integrated
crossover control with dead time. The dead time can be set by a
single external resistor.
The A3930 and A3931 only differ in their response to the all-zero
Selection Guide
Part Number
A3930KJP-T
A3931KJP-T
Option
Hall short detection
Prepositioning
Packing
250 pieces/tray
Terminals
48
Package
LQFP surface mount
Absolute Maximum Ratings
Parameter
Load Supply Voltage
Logic Input/Output Voltage
Symbol
V
BB
V
RESET
V
GHx
V
GLx
V
Cx
VBB pin
Conditions
RESET pin input
Remaining logic pins
GHA, GHB, and GHC pins
GLA, GLB, and GLC pins
CA, CB, and CC pins
SA, SB, and SC pins
CSP, CSN, and LSS pins
CSO, VDSTH pins
VDRAIN pin
Min.
–0.3
–0.3
–0.3
V
Sx
–5
–
–5
–4
–0.3
–
–40
–
–55
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
Max.
50
6
7
V
Sx
+ 15
16
V
Sx
+ 15
45
6.5
6.5
55
135
150
150
Units
V
V
V
V
V
V
V
V
V
°C
°C
°C
Output Voltage Range
V
Sx
Operating Temperature Range (K)
Junction Temperature
Storage Temperature Range
T
A
T
J
T
S
Subject to Change Without Notice
April 6, 2006
Preliminary Data Sheet
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
Functional Block Diagram
VBAT+
CP
VBB
CP2
CP1
P
QV5
V5BD
+5V Ref
V5
CV5
Charge
Pump
Regulator
VREG
CREG
VDRAIN
MODE
Phase A of three phases
COAST
Charge
Pump
CA
CBOOTA
H1
H2
H3
V5
BRAKE
RESET
Boostrap
Monitor
GHA
DIR
High-Side
Drive
RGHA
B
C
H1
Control
Logic
SA
H2
A
H3
VREG
Low-Side
Drive
GLA
RGLA
RDEAD
LSS
PWM
TACHO
TEST
R
DIRO
Q
S
ESF
Diagnostics and
Protection
–UVLO
–TSD
–Short to Supply
–Short to Ground
–Shorted Winding
–Low Load
Pad
VDSTH
RT
RC
CT
Blanking
OSC
CSP
RSENSE
CSN
FF1
FF2
REF
P
CSOUT
AGND
Subject to Change Without Notice
April 6, 2006
Preliminary Data Sheet
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS
at T
J
= –40°C to 150°C, V
BB
= 7 to 45 V, unless otherwise noted
1
Characteristics
Supply and Reference
VBB Functional Operating Range
6
VBB Quiescent Current
V5 Quiescent Current
VREG Output Voltage
Symbol
V
BB
I
BBQ
I
BBS
I
V5Q
V
REG
Test Conditions
Function correct, parameters not
guaranteed
RESET = High, outputs = Low
RESET = Low, sleep mode
RESET = High, outputs = Low
V
BB
> 7.5 V,
I
REG
= 0 to 15 mA
6 V < V
BB
< 7.5 V
I
REG
= 0 to 15 mA
5.5 V < V
BB
< 6 V,
I
REG
< 10 mA
I
D
= 10 mA
I
D
= 100 mA
r
D(100 mA)
= (V
fBOOT(150 mA)
–
V
fBOOT(50 mA)
) / 100 mA
Min.
5.5
–
–
–
12.5
2 × V
BB
–2.5
9
0.4
1.5
6
250
–
40
4.75
–
–
–
–
3
5
1
1.5
–
–
V
Cx
– 0.2
V
REG
–
0.2
From input change to unloaded gate
output change
R
DEAD
= 5 kΩ
R
DEAD
= 50 kΩ
R
DEAD
= 400 kΩ
RDEAD = tied to V5
–
–
815
–
–
Typ.
–
11
–
–
13
–
10
0.7
2.2
10
500
200
–
5
–
–
60
40
4
6
1.5
2.3
–500
850
–
–
90
180
960
3.3
6
Max.
50
14
10
5
13.75
–
–
1.0
2.8
20
750
–
–
5.25
1
–2
–
–
5
7
2
3
–
–
–
–
150
–
1110
–
–
Units
V
mA
μA
mA
V
V
V
V
V
Ω
mA
μA
μA
V
V
mA
ns
ns
Ω
Ω
Ω
Ω
mA
mA
V
V
ns
ns
ns
μs
μs
Bootstrap Diode Forward Voltage
Bootstrap Diode Resistance
Bootstrap Diode Current Limit
Top-off Charge Pump Current Limit
Cx Top-off Charge Pump Source Current
V5 Output Voltage
V
BE
of External Transistor QV5
V5BD Base Drive Capability for QV5
2
Gate Output Drive
Turn-On Rise Time
Turn-Off Fall Time
Pull-Up On Resistance
Pull-Down On Resistance
Short-Circuit Current – Source
2
Short-Circuit Current – Sink
GHx Output Voltage
GLx Output Voltage
Turn-Off Propagation Delay
V
fBOOT
r
D
I
DBOOT
I
TOCPM
I
Cx
V
5
V
BEEXT
I
5BD
t
r
t
f
R
DS(on)UP
R
DS(on)DN
I
SC(source)
I
SC(sink)
V
GHx
V
GLx
t
p(off)
V
Cx
-V
Sx
= 8 V, V
BB
= 14 V, GHx = High
C
LOAD
= 3300 pF, 20% to 80% points
C
LOAD
= 3300 pF, 80% to 20% points
T
J
= 25°C,
I
GHx
= –150 mA
T
J
= 150°C,
I
GHx
= –150 mA
T
J
= 25°C,
I
GLx
= 150 mA
T
J
= 150°C,
I
GLx
= 150 mA
T
J
= 25°C
T
J
= 25°C
t
w
< 10
μs
Bootstrap capacitor fully charged
Dead Time (turn-off to turn-on delay)
t
DEAD
Continued on the next page...
Preliminary Data Sheet
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
Subject to Change Without Notice
April 6, 2006
A3930
and
A3931
Automotive 3-Phase BLDC Controller
and MOSFET Driver
ELECTRICAL CHARACTERISTICS
at T
J
= –40°C to 150°C, V
BB
= 7 to 45 V, unless otherwise noted
1
Characteristics
Logic Inputs and Outputs
FFx Fault Output (Open Drain)
FFx Fault Output Leakage Current
2
TACHO and DIRO Output High Voltage
TACHO and DIRO Output Low Voltage
Input Low Voltage
Input High Voltage (Except RESET)
RESET Input High Voltage
Input Hysteresis
Input Current (Except H1, H2, H3, and
RESET)
2
RESET Input Pull-Down Resistor
Hx Input Pull-Up Resistor
Current Sense Differential Amplifier
Input Bias Current
2
Input Offset Current
2
CSP Input Resistance
CSN Input Resistance
Differential Input Voltage
Output Offset Voltage
Output Offset Voltage Drift
Input Common Mode Range
Differential Input Voltage Gain
Low Output Voltage Error
DC Common Mode Gain
Source Resistance
Output Dynamic Range
Output Current – Sink
Output Current – Source
2
Supply Rejection
Small Signal 3dB Bandwidth Frequency
Settling Time
Symbol
V
OL
I
OH
V
OH
V
OL
V
IL
V
IH
V
IHR
V
IHys
I
IN
R
PD
R
PU
I
IBS
I
IOS
R
CSP
R
CSN
V
ID
V
OOS
V
OOS(Δt)
V
CM
A
V
V
err
A
CMdc
r
CSOUT
V
CSOUT
I
CSOUT(sink)
I
CSOUT(source)
PSRR
f
3dB
t
SETTLE
V
IN
= 5 V
V
IN
= 0 V
CSP = CSN = 0 V
CSP = CSN = 0 V
Measured with respect to AGND
Measured with respect to AGND
V
ID
= CSP – CSN, –1.3 V < CSP < 4 V,
–1.3 V < CSN < 4 V
CSP = CSN = 0 V
CSP = CSN = 0 V
CSP = CSN
40 mV < V
ID
< 175 mV, V
CM
in range
0 < V
ID
< 40 mV,
V
CSOUT
= (19 × V
ID
) + V
OOS
+ V
err
CSP = CSN = 200 mV
V
CSOUT
= 2.0 V,
I
CSOUT
= [TBD]
μA
–100
μA
< I
CSOUT
< 100
μA
V
CSOUT
= 2 V ±5%
V
CSOUT
= 2 V ±5%
CSP = CSN = AGND, 0 to 300 kHz
V
ID
=10 mVpp
To within 10%, V
CSOUT
= 1 Vpp square
wave
Test Conditions
I
OL
= 1 mA, fault asserted
V
O
= 5 V, fault not asserted
I
OH
= –1 mA
I
OL
= 1 mA
Min.
–
–1
V
5
– 1 V
–
–
2
2.2
300
–1
–
–
–95
–20
–
–
0
150
–
–1.5
18.2
–20
–
–
0.1
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
500
–
50
100
–145
–
80
4
–
375
100
–
19
–
–30
30
–
1
–19
45
1.6
400
Max.
0.4
1
–
0.4
0.8
–
–
–
1
–
–
–205
20
–
–
200
600
–
4
19.4
20
–
–
4.8
–
–
–
–
–
Units
V
μA
V
V
V
V
V
mV
μA
kΩ
kΩ
μA
μA
kΩ
kΩ
mV
mV
μV/°C
V
V/V
mV
dB
Ω
V
mA
mA
dB
MHz
ns
Continued on the next page…
Subject to Change Without Notice
April 6, 2006
Preliminary Data Sheet
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
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