Pre-Production
FM25L512
512Kb F-RAM Serial 3V Memory
Features
512K bit Ferroelectric Nonvolatile RAM
•
Organized as 65,536 x 8 bits
•
Unlimited Read/Write Cycles
•
10 Year Data Retention
•
NoDelay™ Writes
•
Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
•
Up to 20 MHz Frequency
•
Direct Hardware Replacement for EEPROM
•
SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Write Protection Scheme
•
Hardware Protection
•
Software Protection
Low Power Consumption
•
Low Voltage Operation 3.0V – 3.6V
•
20
µA
Standby Current
Industry Standard Configurations
•
Industrial Temperature -40°C to +85°C
•
8-pin “Green”/RoHS TDFN Package
•
Footprint Compatible with SOIC-8 (see pg 12)
Description
The FM25L512 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25L512 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, F-RAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25L512 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L512 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L512 uses the high-speed SPI
bus, which enhances the high-speed write capability
of F-RAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
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Pin Configuration
Top View
/CS
SO
1
2
3
4
8
VDD
SCK
SI
7
6
5
/HOLD
/WP
VSS
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (3.0 to 3.6V)
Ground
Ordering Information
FM25L512-DG*
FM25L512-DGTR*
8-pin “Green”/RoHS TDFN
8-pin “Green”/RoHS TDFN
in Tape & Reel
* Last time buy Nov. 2009.
This is a product in the pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if any
specification changes are made.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Rev. 2.2
Oct. 2009
Page 1 of 13
FM25L512
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
8192 x 64
FRAM Array
Instruction Register
Pin Descriptions
Pin Name
/CS
SCK
/HOLD
/WP
SI
SO
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F
SI
Data I/O Register
3
SO
Nonvolatile Status
Register
Address Register
Counter
16
8
Figure 1. Block Diagram
I/O
Input
Input
Input
Input
Input
Output
VDD
VSS
Supply
Supply
Description
Chip Select: This active low input activates the device. When high, the device enters
low-power standby mode, ignores other inputs, and all outputs are tri-stated. When
low, the device internally activates the SCK signal. A falling edge on /CS must occur
prior to every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on
the rising edge and outputs occur on the falling edge. Since the device is static, the
clock frequency may be any value between 0 and 20 MHz and may be interrupted at
any time.
Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation
for another task. When /HOLD is low, the current operation is suspended. The device
ignores any transition on SCK or /CS. All transitions on /HOLD must occur while
SCK is low.
Write Protect: This active low pin prevents write operations to the Status Register
only. A complete explanation of write protection is provided on pages 6 and 7.
Serial Input: All data is input to the device on this pin. The pin is sampled on the
rising edge of SCK and is ignored at other times. It should always be driven to a valid
logic level to meet I
DD
specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: This is the data output pin. It is driven during a read and remains tri-
stated at all other times including when /HOLD is low. Data transitions are driven on
the falling edge of the serial clock.
* SO may be connected to SI for a single pin data interface.
Power Supply (3.0V to 3.6V)
Ground
Rev. 2.2
Oct. 2009
Page 2 of 13
FM25L512
Overview
The FM25L512 is a serial F-RAM memory. The
memory array is logically organized as 65,536 x 8
and is accessed using an industry standard Serial
Peripheral Interface or SPI bus. Functional operation
of the F-RAM is similar to serial EEPROMs. The
major differences between the FM25L512 and a
serial EEPROM with the same pinout are the F-
RAM’s superior write performance, unlimited
endurance, and lower power consumption.
microcontroller. Many common microcontrollers
have hardware SPI ports allowing a direct interface.
It is quite simple to emulate the port using ordinary
port pins for microcontrollers that do not. The
FM25L512 operates in SPI Mode 0 and 3.
The SPI interface uses a total of four pins: clock,
data-in, data-out, and chip select. A typical system
configuration uses one or more FM25L512 devices
with a microcontroller that has a dedicated SPI port,
as Figure 2 illustrates. Note that the clock, data-in,
and data-out pins are common among all devices.
The Chip Select and Hold pins must be driven
separately for each FM25L512 device.
For a microcontroller that has no dedicated SPI bus, a
general purpose port may be used. To reduce
hardware resources on the controller, it is possible to
connect the two data pins together and tie off the
Hold pin. Figure 3 shows a configuration that uses
only three pins.
Protocol Overview
The SPI interface is a synchronous serial interface
using clock and data pins. It is intended to support
multiple devices on the bus. Each device is activated
using a chip select. Once chip select is activated by
the bus master, the FM25L512 will begin monitoring
the clock and data lines. The relationship between the
falling edge of /CS, the clock and data is dictated by
the SPI mode. The device will make a determination
of the SPI mode on the falling edge of each chip
select. While there are four such modes, the
FM25L512 supports only modes 0 and 3. Figure 4
shows the required signal relationships for modes 0
and 3. For both modes, data is clocked into the
FM25L512 on the rising edge of SCK and data is
expected on the first rising edge after /CS goes
active. If the clock starts from a high state, it will fall
prior to the first data transfer in order to create the
first rising edge.
The SPI protocol is controlled by op-codes. These
op-codes specify the commands to the device. After
/CS is activated the first byte transferred from the bus
master is the op-code. Following the op-code, any
addresses and data are then transferred.
Certain op-codes are commands with no subsequent
data transfer. The /CS must go inactive after an
operation is complete and before a new op-code can
be issued. There is one valid op-code only per active
chip select.
Memory Architecture
When accessing the FM25L512, the user addresses
64K locations of 8 data bits each. These data bits are
shifted serially. The addresses are accessed using the
SPI protocol, which includes a chip select (to permit
multiple devices on the bus), an op-code, and a two-
byte address. The complete address of 16-bits
specifies each byte address uniquely.
Most functions of the FM25L512 either are
controlled by the SPI interface or are handled
automatically by on-board circuitry. The access time
for memory operation is essentially zero, beyond the
time needed for the serial protocol. That is, the
memory is read or written at the speed of the SPI bus.
Unlike an EEPROM, it is not necessary to poll the
device for a ready condition since writes occur at bus
speed. So, by the time a new bus transaction can be
shifted into the device, a write operation will be
complete. This is explained in more detail in the
interface section.
Users expect several obvious system benefits from
the FM25L512 due to its fast write cycle and high
endurance as compared to EEPROM. In addition
there are less obvious benefits as well. For example
in a high noise environment, the fast-write operation
is less susceptible to corruption than an EEPROM
since it is completed quickly. By contrast, an
EEPROM requiring milliseconds to write is
vulnerable to noise during much of the cycle.
Note that the FM25L512 contains no power
management circuits other than a simple internal
power-on reset. It is the user’s responsibility to
ensure that V
DD
is within datasheet tolerances to
prevent incorrect operation.
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Serial Peripheral Interface – SPI Bus
The FM25L512 employs a Serial Peripheral Interface
(SPI) bus. It is specified to operate at speeds up to
20MHz. This high-speed serial bus provides high
performance serial communication to a host
Rev. 2.2
Oct. 2009
Page 3 of 13
FM25L512
SPI Mode 0: CPOL=0, CPHA=0
SPI Mode 3: CPOL=1, CPHA=1
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Figure 2. 1Mbit System Configuration with SPI port
Figure 3. System Configuration without SPI port
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 4. SPI Modes 0 & 3
Rev. 2.2
Oct. 2009
Page 4 of 13
FM25L512
Power Up to First Access
The FM25L512 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter t
PU
, which is the minimum time
from V
DD
(min) to the first /CS low.
Data Transfer
All data transfers to and from the FM25L512 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L512. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name
Description
Set Write Enable Latch
WREN
Write Disable
WRDI
Read Status Register
RDSR
Write Status Register
WRSR
Read Memory Data
READ
WRITE
Write Memory Data
Op-code
WREN - Set Write Enable Latch
The FM25L512 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the Status
Register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the
latch. WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will be automatically cleared on the rising
edge of /CS following a WRDI, a WRSR, or a
WRITE operation. This prevents further writes to
the Status Register or the F-RAM array without
another WREN command. Figure 5 below illustrates
the WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 6 illustrates the WRDI command bus
configuration.
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0000
0000
0000
0000
0000
0000
0110b
0100b
0101b
0001b
0011b
0010b
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
1
0
SO
Hi-Z
Figure 5. WREN Bus Configuration
Rev. 2.2
Oct. 2009
Page 5 of 13
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