Product Specification
PE3512
Product Description
The PE3512 is a high-performance static UltraCMOS™
prescaler with a fixed divide ratio of 4. Its operating frequency
range is DC to 1500 MHz. The PE3512 operates on a nominal
3 V supply and draws only 8 mA. The input and output
interfaces support both AC-coupled, low-Z RF as well as direct
connection to low voltage positive logic devices. It is packaged
in a small 6-lead SC-70 and is ideal for frequency scaling
solutions
The PE3512 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
1500 MHz Low Power UltraCMOS™
Divide-by-4 Prescaler
Features
•
DC to 1500 MHz operation
•
Fixed divide ratio of 4
•
Low-power consumption: 8 mA typical
@ 3V
•
RF or LV Digital Interface
•
Ultra-small package: 6-lead SC-70
IN
Pre-Amp
CLK QB
CLK QB
Table 1. Electrical Specifications
(Z
S
= Z
L
= 50
Ω
)
V
DD
= 3.0 V, -40° C
≤
T
A
≤
85° C, unless otherwise specified
Parameter
Supply Voltage
Supply Current
Input Frequency (F
in
)
O
Conditions
bs
o
Output
Buffer
D
Q
D
Q
le
OUT
Figure 1. Functional Schematic Diagram
Minimum
2.85
te
Typical
3.0
8
DC
-10
-3
2
Figure 2. Package Type
6-lead SC70
Maximum
3.15
12
1500
+10
Units
V
mA
MHz
dBm
dBm
dBm
DC <
Fin
≤
1000 MHz (Note 1)
Input Power (P
in
)
1000 MHz < Fin
≤
1500
Output Power (P
out
)
Note 1:
DC < Fin
≤
1500 MHz
CMOS logic levels can be used to drive the reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. The
input edge rate should be faster than 80mV/ns from DC - 10 MHz.
Document No. 70-0107-06
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©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE3512
Product Specification
Table 2. DC Electrical Characteristics (-40° C
≤
T
A
≤
85° C)
Symbol
V
IH
V
IL
V
OH
V
OL
Parameter
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Condition
2.7 V
≤
V
DD
≤
3.3 V
2.7 V
≤
V
DD
≤
3.3 V
V
DD
= 2.7 V; I
OH
= 2.9 mA
V
DD
= 2.7 V; I
OL
= 2.6 mA
Typical
2.0
0.8
2.2
0.4
Unit
V
V
V
V
Table 3. AC Characteristics (-40° C
≤
T
A
≤
85° C)
Symbol
t
PHL
t
PLH
t
r
t
f
Parameter
Propagation Delay
(High to Low)
Propagation Delay
(Low to High)
Output Rise Time
(10% to 90%)
Output Fall Time
(90% to 10%)
Condition*
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
50 MHz Pulse Train Input;
C
L
= 10 pF, R
L
= 500
Ω
Typical
3.0
3.2
Unit
ns
ns
ns
ns
Table 4. Typical Output Swing (V
DD
= 2.7 V)
Frequency
50 MHz
500 MHz
1500 MHz
Condition
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
200 mVp-p Sinusoidal Input;
C
L
= 10 pF, R
L
= 500
Ω
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
O
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UltraCMOS™ RFIC Solutions
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
bs
o
Typical
2.3
2.2
1.7
le
Unit
Vp-p
Vp-p
Vp-p
* See figure 5 for AC test circuit
te
2.0
2.0
PE3512
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 6.
Latch-Up Avoidance
pin 1
NC
GND
IN
1
6
OUT
GND
V
DD
.
512
SC-70
2
5
3
4
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Description
Table 5. Pin Descriptions
Pin
No.
1
2
Pin
Name
N/C
GND
Device Functional Considerations
The
PE3512
divides an input signal, up to a
frequency of 1500 MHz, by a factor of four thereby
producing an output frequency at one-fourth the
input frequency. To work properly with low
impedance, ground referenced interfaces, the
input and output signals (pins 3 & 6) must be AC
coupled via an external capacitor, as shown in the
test circuit in Figure 4.
The ground pattern on the board should be made
as wide as possible to minimize ground
impedance. See Figure 9 for a layout example.
No Connect. This pin should be left open.
Ground pin. Ground pattern on the board
should be as wide as possible to reduce
ground impedance.
Input signal pin. DC blocking capacitor
required (100 pF typical).
Power supply pin. Bypassing is required.
Ground pin.
Divided frequency output pin. DC blocking
capacitor required (100 pF typical).
3
4
5
6
IN
V
DD
GND
OUT
Table 6. Absolute Maximum Ratings
Symbol
V
DD
P
in
T
ST
T
OP
V
ESD
Parameter/Conditions
Supply voltage
Input Power
Storage temperature
range
Min
O
-65
-40
Operating temperature
range
ESD voltage (Human
Body Model)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
bs
o
Max
4.0
13
Units
V
dBm
°C
°C
V
150
85
2000
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PE3512
Product Specification
Figure 4. Test Circuit Block Diagram
Spectrum
Analyzer
1 N/C
2 GND
50 Ohm
100 pF
VDD
3V +/- 0.15 V
100 pF
1000 pF
3 IN
OUT 6
100 pF
GND 5
VDD 4
50 Ohm
PE3512
Signal
Generator
Figure 5. AC Test Circuit
Pulse
Generator
O
bs
o
V
DD
PE3512
C
L
R
T
R
L
Document No. 70-0107-06
│
UltraCMOS™ RFIC Solutions
R
T =
Zout of pulse generator
(usually 50 ohm)
©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
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PE3512
Product Specification
Typical Performance Data: V
DD
= 3.0 V
Figure 6. Input Sensitivity
Figure 7. Device Current
Figure 8. Output Power
O
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©2003-2008 Peregrine Semiconductor Corp. All rights reserved.
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Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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te
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