CMP3217AAx-E
Document Title
2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
CMOS LPRAM
Revision History
Revision
No.
0.0
Initial Draft
Add the page write timing
Revise the pin description
Minor changes
Add wafer level products
Revise the page speed
Add tCP=10ns in AC characteristics
Change the page speed(20ns 25ns) and ISB1(70uA 100uA)
Minor changes
Change the ISB1(100uA 120uA)
Change the MRS set condition
Minor changes
Modified functional description & MRS update timing
Minor Changes
Added G(Pb-Free) and H(Pb-Free & Halogen Free) descriptions
History
Draft date
Jun. 19
th
, 2003
Remark
Preliminary
0.1
Jul. 11
th
, 2003
Preliminary
0.2
Nov. 10
th
, 2003
Preliminary
0.3
Jan. 30
th
, 2004
Preliminary
0.4
0.5
Feb. 27
th
, 2004
Mar. 18
th
, 2004
Preliminary
Preliminary
0.6
0.7
Nov. 8
th
, 2004
Nov. 1
st
, 2005
Final
Final
1
Revision 0.7
Nov. 2005
CMP3217AAx-E
FEATURES
•
Process Technology : Full CMOS
• Organization : 2M x 16
• Power Supply Voltage : 2.7~3.3V
• Low Power & Page Modes
CMP3217AA1 : support the PASR/DPD function
CMP3217AA2 : support the Direct DPD function
CMP3217AA4 : support the PASR/DPD/PAGE function
CMP3217AA5 : support the Direct DPD/PAGE function
CMOS LPRAM
2M x 16 bit Super Low Power and Low Voltage Full CMOS RAM
• Three state output and TTL Compatible
• Package Type : 48-FBGA-6.00x8.00 mm
2
• Separated I/O power(VCCQ) & Core Power(VCC)
• Page read/write operation by 16 words
(CMP3217AA4, CMP3217AA5)
• DPD mode by using MRS only
(CMP3217AA1, CMP3217AA4)
• Direct DPD mode when /ZZ goes low
(CMP3217AA2, CMP3217AA5)
PRODUCT FAMILY
Operating
Temperature
Operating
Voltage (V)
Speed
Min. Typ. Max.
CMP3217AAx-F60E
CMP3217AAx-F70E
Extended
(-25~85’C)
60ns
70ns
Typ.
1.5mA
Power Dissipation
ICC1
f = 1MHz
Max.
3mA
ICC2
f = fmax
Typ.
15mA
12mA
Max.
25mA
ISB1
(CMOS Standby
Current)
Typ.
60uA
Max.
120uA
Product Family
2.7
3.0
3.3
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and T
A
= 25C.
2.
F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free
& Halogen Free),
W=WAFER
PIN DESCRIPTION
1
2
3
4
5
6
FUNCTIONAL BLOCK DIAGRAM
Precharge circuit.
A
B
C
D
E
F
G
H
/LB
I/O9
/OE
/UB
A0
A3
A1
A4
A2
/CS
/ZZ
I/O1
Clk gen.
VCC
VSS
Memory array
I/O10
VSS
I/O11
I/O12
A5
A17
A6
A7
A16
I/O2
I/O4
I/O5
I/O3
VCC
VSS
Row
Addresses
Row
select
VCCQ
I/O15
I/O16
A18
I/O13
I/O14
A19
A8
DNU
A14
A12
A9
A15
A13
A10
I/O6
I/O7
I/O8
I/O1~I/O8
Data
cont
I/O Circuit
Column select
WE
A11
A20
I/O9~I/O16
Data
cont
48-FBGA : Top View(Ball Down)
Data
cont
Column Addresses
Name
/ZZ
/CS
/OE
/WE
A0~A20
I/O1~I/O16
Function
Low Power Modes
Chip Select Input
Output Enable Input
Write Enable Input
Address Inputs
Data Inputs/Outputs
Name
VCC
VCCQ
VSS
/UB
/LB
DNU
Function
Core Power
I/O Power
Ground
Upper Byte(I/O9~16)
Lower Byte(I/O 1~8)
Do Not Use
/CS
/OE
/WE
/UB
/LB
/ZZ
Control Logic
2
Revision 0.7
Nov. 2005
CMP3217AAx-E
PRODUCT LIST
Extended Temperature Products(-25~85’C)
Part Name
CMP3217AAx-F60E
CMP3217AAx-F70E
1.
F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free
& Halogen Free),
W=WAFER
CMOS LPRAM
Function
48-FBGA, 60ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
48-FBGA, 70ns, VCC=3.0V, VCCQ=3.0V(2.5V,1.8V)
FUNCTIONAL DESCRIPTION
/CS
H
X
1)
H
X
1)
L
/ZZ
H
L
L
H
H
H
/OE
X
1)
X
1)
X
1)
X
1)
H
H
/WE
X
1)
X
1)
X
1)
X
1)
H
H
/LB
X
1)
X
1)
X
1)
H
L
X
1)
L
L
L
H
X
1)
L
H
H
L
L
H
L
1. X means don’t care.(Must be low or high state)
2. In case of CMP3217AA2 & CMP3217AA5 product
3. In case of CMP3217AA1 & CMP3217AA4 product
/UB
X
1)
X
1)
X
1)
H
X
1)
L
H
L
L
H
L
L
I/O1-8
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
I/O9-16
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
Mode
Deselected
Deselected
Deselected
Deselected
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
Lower Byte Write
Upper Byte Write
Word Write
Power
Standby
Direct DPD
2)
Low Power Modes
3)
Standby
Active
Active
Active
Active
Active
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
, V
OUT
Vcc
P
D
T
STG
T
A
Ratings
-0.2 to Vcc+0.3V
-0.2 to 3.6
1.0
-65 to 150
-25 to 85
Unit
V
V
W
’C
’C
1. Str es s e s g r e ate r tha n th o s e l i st e d u n d er “ A bsolute Maxim um Ratings” may cause permanent dam age to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
I/O operating voltage (VCCQ
≤
VCC)
Ground
Input high voltage
Input low voltage
Symbol
V
CC
V
CCQ
V
SS
V
IH
V
IL
CMP3217AA
Min
2.7
2.7
0
0.8VCCQ
-0.2
3)
Max
3.3
3.3
0
VCC+0.2
2)
0.2VCCQ
Min
2.7
2.25
0
0.8VCCQ
-0.2
3)
Max
3.3
2.75
0
VCC+0.2
2)
0.2VCCQ
Min
2.7
1.65
0
0.8VCCQ
-0.2
3)
Max
3.3
1.95
0
VCC+0.2
2)
0.2VCCQ
Unit
V
V
V
V
V
Note :
1.T
A
=-25 to 85’C, otherwise specified.
2. Overshoot : Vcc+1.0V in case of pulse width≤20ns.
3. Undershoot : -1.0V in case of pulse width≤20ns.
4. Overshoot and undershoot are sampled, not 100% tested.
3
Revision 0.7
Nov. 2005
CMP3217AAx-E
CAPACITANCE
1)
(f=1MHz , T
A
=25’C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested.
CMOS LPRAM
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Symbol
I
LI
I
LO
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
V
OL
V
OH
I
SB
I
SB1
I
SB0
Low Power Modes
I
SB0a
I
SB0b
I
SB0c
V
IN
=V
SS
to V
CC
/CS=V
IH
, /ZZ=V
IH
, /OE=V
IH
or /WE=V
IL
, V
IO
=V
SS
to V
CC
Cycle time=1us, 100%duty, I
IO
=0mA, /CS≤0.2V, /ZZ=V
IH
,
V
IN
≤0.2V
or V
IN
≥V
CC
-0.2V
Cycle time=Min, I
IO
=0mA, 100% duty, /CS=V
IL
, /ZZ=V
IH
,
V
IN
=V
IL
or V
IH
I
OL
=0.5mA
I
OH
=-0.5mA
/CS=V
IH
, /ZZ=V
IH
, Other inputs=V
IH
or V
IL
/CS≥V
CC
-0.2V, /ZZ≥V
CC
-0.2V, Other inputs=0~V
CC
/ZZ≤0.2V, Other inputs=0~V
CC
, No refresh(DPD)
/ZZ≤0.2V, Other inputs=0~V
CC
, ¼ refresh area selection
/ZZ≤0.2V, Other inputs=0~V
CC
, ½ refresh area selection
/ZZ≤0.2V, Other inputs=0~V
CC
, All refresh area selection
0.8VCCQ
-
-
-
-
-
-
-
-
-
-
-
-
0.3
120
10
75
90
120
Test Conditions
Min
-1
-1
-
-
Typ
-
-
-
-
Max
1
1
3
25
0.2VCCQ
Unit
uA
uA
mA
mA
V
V
mA
uA
uA
uA
uA
uA
4
Revision 0.7
Nov. 2005
CMP3217AAx-E
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.2 to VCC-0.2V
Input rising and falling time : 5ns
Input and output reference voltage : 0.5*VCCQ
Output load(see right) : C
L
=30pF+1TTL
30pf
CMOS LPRAM
1TTL
AC CHARACTERISTICS
(V
CC
=2.7V~3.3V, Extended product : T
A
=-25 to 85’C)
Speed Bins
Parameter List
Symbol
Min
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
/UB, /LB Access Time
Read
Chip Select to Low-Z Output
/UB, /LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High- Z Output
/UB, /LB Disable to High- Z Output
Output Disable to High- Z Output
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
/UB, /LB Valid to End of Write
Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Page Mode Cycle Time
Page
Page Mode Address Access Time
Maximum Cycle Time
/CS High Pulse Width
tRC
tAA
tCO
tOE
tBA
tLZ
tBLZ
tOLZ
tHZ
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
tPC
tPAA
tMRC
tCP
60
-
-
-
-
10
10
5
0
0
0
5
60
50
0
50
50
50
0
0
20
0
5
25
-
-
10
60ns
Max
20k
60
60
25
60
-
-
-
5
5
5
-
20k
-
-
-
-
-
-
5
-
-
-
-
25
20k
-
Min
70
-
-
-
-
10
10
5
0
0
0
5
70
60
0
60
60
50
0
0
20
0
5
25
-
-
10
70ns
Max
20k
70
70
25
70
-
-
-
5
5
5
-
20k
-
-
-
-
-
-
5
-
-
-
-
25
20k
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
5
Revision 0.7
Nov. 2005
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
