EtronTech
Features
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Fast access time from clock: 5/6/6/6/7 ns
Fast clock rate: 166/143/133/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
Auto Refresh and Self Refresh
4096 refresh cycles/64ms
CKE power down mode
Single +3.3V
±
0.3V power supply
Interface: LVTTL
54-pin 400 mil plastic TSOP II package
EM638165
Preliminary (Rev 0.4, 6/2000)
4Mega x 16 Synchronous DRAM (SDRAM)
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE#
CAS#
RAS#
CS#
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC/RFU
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
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Overview
The EM638165 SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The EM638165 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
Key Specifications
EM638165
-
6/7/7.5/8/10
6/7/7.5/8/10 ns
5/6/6/6/7 ns
42/48/48/48/50 ns
60/68/68/68/80 ns
t
CK3
t
AC3
t
RAS
t
RC
Clock Cycle time(min.)
Access time from CLK(max.)
Row Active time(max.)
Row Cycle time(min.)
Ordering Information
Part Number
EM638165TS-6
EM638165TS-7
EM638165TS-7.5
EM638165TS-8
EM638165TS-10
Frequency
166MHz
143MHz
133MHz
125MHz
100MHz
Package
TSOP II
TSOP II
TSOP II
TSOP II
TSOP II
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345
FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EtronTech
Block Diagram
EM638165
CLOCK
CLOCK
CLOCL
BUFFER
BUFFER
CKE
Decoder
CS#
RAS#
CAS#
WE#
UDQM
LDQM
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
1MX16
CELL ARRAY
(BANK #A)
Column Decoder
COLUMN
COUNTER
Buffer
DQ0
|
DQ15
MODE
REGISTER
Decoder
A0
A11
BA0
BA1
~
ADDRESS
BUFFER
1MX16
CELL ARRAY
(BANK #B)
Column Decoder
REFRESH
COUNTER
1MX16
CELL ARRAY
(BANK #C)
Column Decoder
Decoder
1MX16
CELL ARRAY
(BANK #D)
Column Decoder
Preliminary
2
Decoder
Rev 0.4
June 2000
EtronTech
Pin Descriptions
Table 1. Pin Details of EM638165
Symbol
CLK
Type
Input
Description
EM638165
Clock:
CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal burst
counter and controls the output registers.
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If
CKE goes low synchronously with clock(set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state
of output and burst address is frozen as long as the CKE remains low. When
both banks are in the idle state, deactivating the clock controls the entry to the
Power Down and Self Refresh modes. CKE is synchronous except after the
device enters Power Down and Self Refresh modes, where CKE becomes
asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low
standby power.
Bank Select:
BA0,BA1 input select the bank for operation.
BA1
0
0
1
1
BA0
0
1
0
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
CKE
Input
BA0,BA1
Input
A0-A11
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row
address A0-A11) and Read/Write command (column address A0-A7 with A10
defining Auto Precharge) to select one location out of the 2M available in the
respective bank. During a Precharge command, A10 is sampled to determine if
both banks are to be precharged (A10 = HIGH). The address inputs also provide
the op-code during a Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH.
CS# provides for external bank selection on systems with multiple banks. It is
considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH," either the BankActivate command or the Precharge command is
selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BS is turned on
to the active state. When the WE# is asserted "LOW," the Precharge command
is selected and the bank designated by BS is switched to the idle state after the
precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges
of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column
access is started by asserting CAS# "LOW." Then, the Read or Write command
is selected by asserting WE# "LOW" or "HIGH."
CS#
Input
RAS#
Input
CAS#
Input
Preliminary
3
Rev 0.4
June 2000
EtronTech
WE#
Input
LDQM,
UDQM
DQ0-DQ15
NC/RFU
V
DDQ
Input
EM638165
Write Enable:
The WE# signal defines the operation commands in conjunction
with the RAS# and CAS# signals and is latched at the positive edges of CLK.
The WE# input is used to select the BankActivate or Precharge command and
Read or Write command.
Data Input/Output Mask:
Controls output buffers in read mode and masks
Input data in write mode.
Input /
Output
-
Supply
Data I/O:
The DQ0-15 input and output data are synchronized with the positive
edges of CLK. The I/Os are maskable during Reads and Writes.
No Connect:
These pins should be left unconnected.
DQ Power:
Provide isolated power to DQs for improved noise immunity.
( 3.3V± 0.3V )
V
SSQ
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.
(0V)
Power Supply:
+3.3V
±
0.3V
Ground
V
DD
V
SS
Supply
Supply
Preliminary
4
Rev 0.4
June 2000
EtronTech
Operation Mode
EM638165
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 2 shows the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
DQM BA
0,1
A
10
A
0-9,11
CS# RAS# CAS# WE#
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
Row address
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
address
(A0 ~ A7)
Column
address
(A0 ~ A7)
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
OP code
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(5)
Active
Any
(PowerDown)
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Active
H
X
H
X
X
X
X
X
X
Note:
1. V=Valid X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
Preliminary
5
Rev 0.4
June 2000
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