19-4792; Rev 2; 5/04
KIT
ATION
EVALU
E
BL
AVAILA
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
General Description
Features
♦
Single +3.3V Supply
♦
Low Jitter: 10ps
♦
Low Power Consumption
190mW (MAX3750)
180mW (MAX3751)
♦
Large Output Signal Swing: >1000mVp-p
♦
Mismatch Tolerant Output Driver Stage
♦
150Ω Differential On-Chip Termination on All Inputs
♦
150Ω On-Chip Back Termination on All Output
Ports
MAX3750/MAX3751
The MAX3750/MAX3751 are +3.3V, Fibre Channel port
bypass ICs that include a high-speed multiplexer and
output buffer stage for hot swapping a storage device.
These devices are optimized for use in a Fibre Channel
arbitrated loop topology.
The MAX3750 has a 2.125Gbps data rate, while the
MAX3751’s data rate is 1.0625Gbps. Total power con-
sumption (including output currents) is low: just 190mW
for the MAX3750 and 180mW for the MAX3751. Low
10ps jitter makes these devices ideal for cascaded
topologies. The output driver circuitry is tolerant of load
mismatches commonly caused by board vias and
inductive connectors. On-chip termination reduces
external part count and simplifies board layout.
Ordering Information
PART
MAX3750CEE
MAX3750CEE†
MAX3751CEE
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 QSOP
16 QSOP
16 QSOP
Applications
2.125Gbps Fibre Channel Arbitrated Loop
1.0625Gbps Fibre Channel Arbitrated Loop
Mass Storage Systems
RAID/JBOD Applications
†Denotes
lead-free package.
Typical Application Circuit
FC-AL
DISK DRIVE
FC-AL
DISK DRIVE
TX
RX
C7
TX
C8
C2
RX
C1
TX
FC-AL
DISK DRIVE
RX
LOUT+
LOUT-
LIN+
LIN-
LOUT+
C5
IN+
IN-
C6
V
CC
3.3V
GND
OUT+
OUT-
LIN+
LIN-
LOUT+
LOUT-
LIN+
LIN-
OUT+
OUT-
MAX3750
MAX3750
MAX3751
SEL
C3
IN+
IN-
C4
V
CC
3.3V
GND
OUT+
OUT-
MAX3750
MAX3750
MAX3751
SEL
MAX3750
MAX3750
MAX3751
SEL
LOUT-
IN+
IN-
V
CC
3.3V
GND
C1–C8 = 100nF
MICROPROCESSOR
THREE MAX3750/MAX3751s CASCADED IN AN FC-AL APPLICATION
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
MAX3750/MAX3751
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
..............................................-0.5V to +5.0V
Voltage at LOUT+, LOUT-,
OUT+, OUT- ..............................(V
CC
- 1.65V) to (V
CC
+ 0.5V)
Current Out of LOUT+, LOUT-, OUT+, OUT- ...................±22mA
Voltage at SEL, LIN+, LIN-, IN+, IN- ..........-0.5V to (V
CC
+ 0.5V)
Differential Voltage at (LIN+ - LIN-), (IN+ - IN-).....................±2V
Continuous Power Dissipation (T
A
= +70°C)
16 QSOP (derate 8.3mW/°C above +70°C) .................667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range ...............................-55°C to 150°C
Lead Soldering Temperature (soldering, 10s).................+300°C
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.)
PARAMETER
Supply Current
Data Input Voltage Swing
Differential Input Impedance
Output Voltage at LOUT± and OUT±
TTL Input Current
TTL Input Low
TTL Input High
Note 1:
Output currents included.
CONDITIONS
MAX3750 (Note 1)
MAX3751 (Note 1)
Total differential signal, peak-to-peak
150Ω load, total differential signal,
peak-to-peak
200
132
1000
-10
-0.3
2
MIN
TYP
57
54
150
MAX
84
78
2200
172
1600
10
0.8
V
CC
+ 0.3
UNITS
mA
mV
Ω
mV
µA
V
V
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
CC
= +3.3V and T
A
= +25°C.)
PARAMETER
Data Rate
Data Input Voltage Swing
Output Edge Speed
IN±
→OUT±,
IN±
→LOUT±
Deterministic Jitter
IN±
→OUT±,
IN±
→LOUT±,
LIN±
→OUT±
Random Jitter
IN±
→OUT±,
IN±
→LOUT±,
LIN±
→OUT±
Prop Delay
IN±
→OUT±,
IN±
→LOUT±,
LIN±
→OUT±
MAX3750
MAX3751
Total differential signal, peak-to-peak
MAX3750
MAX3751
MAX3750, peak-to-peak (Notes 2, 4)
MAX3751, peak-to-peak (Notes 3, 4)
MAX3750, RMS (Note 2)
MAX3751, RMS (Note 3)
MAX3750
MAX3751
300
442
10
10
1.6
1.6
200
CONDITIONS
MIN
TYP
2.125
1.0625
2200
160
325
MAX
UNITS
Gbps
mV
ps
ps
ps
ps
Note 2:
Input t
R
and t
F
< 150ps, 20% to 80%.
Note 3:
Input t
R
and t
F
< 300ps, 20% to 80%.
Note 4:
Deterministic jitter is measured with 20 bits of the k28.5 pattern (00111110101100000101).
2
_______________________________________________________________________________________
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
MAX3750/MAX3751
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
58
SUPPLY CURRENT (mA)
57
MAX3750
56
55
54
MAX3751
53
52
51
50
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
MAX3750/51 toc01
59
Pin Description
PIN
1, 4, 5, 8, 16
2
3
6
7
9
10
11
12, 13
14
15
NAME
GND
LOUT+
LOUT-
OUT+
OUT-
SEL
LIN-
LIN+
V
CC
IN-
IN+
Electrical Ground
Noninverted Port Data Output
Inverted Port Data Output
Noninverted Data Output
Inverted Data Output
Select Input:
SEL = Low: IN±
→
OUT±
SEL = High: LIN±
→
OUT±
Inverted Port Data Input
Noninverted Port Data Input
Positive Supply Voltage
Inverted Data Input
Noninverted Data Input
FUNCTION
_______________________________________________________________________________________
3
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
MAX3750/MAX3751
_________________Circuit Description
A simplified block diagram of the single port bypass is
shown in Figure 1. IN+ and IN- drive an input buffer
(INBUFF) with 150Ω of internal differential input termi-
nation. INBUFF drives an output buffer (LOBUFF) and
an input to a multiplexer (MUX).
A low TTL input at SEL selects the signal path of
INBUFF through MUX to the output buffer (OUTBUFF).
When SEL has a high TTL logic level present the signal
path is into LIBUFF, through MUX, to OUTBUFF.
Layout Techniques
The MAX3750/MAX3751 are high-frequency products.
The performance of the circuit is largely dependent
upon layout of the circuit board. Use a multilayer circuit
board with dedicated ground and V
CC
planes. Power
supplies should be capacitively bypassed to the
ground plane with surface-mount capacitors placed
near the power-supply pins.
Low-Frequency Cutoff
The low-frequency cutoff is determined by the input
resistance and the coupling capacitor as illustrated by
the following equation:
f
C
= 1 / (2πRC)
In a typical system where R = 150Ω and C = 100nF,
resulting in f
C
= 10kHz.
LOUT+
LOUT-
LIN+
LOBUFF
LIN-
LIBUFF
OUTBUFF
IN+
INBUFF
MUX
D0
IN-
D1
SEL
Q
OUT-
V
CC
OUT+
MAX3750
MAX3751
TTLIN
GND
SEL
NOTE: SEE INTERNAL INPUT/OUTPUT SCHEMATICS FOR DETAILED TERMINATIONS (FIGURES 2–5).
Figure 1. MAX3750/MAX3751 Block Diagram
4
_______________________________________________________________________________________
+3.3V, 2.125Gbps/1.0625Gbps
Fibre Channel Port Bypass ICs
MAX3750/MAX3751
V
CC
ESD
STRUCTURES
(L)OUT+
V
CC
75Ω
75Ω
(L)OUT-
SEL
ESD
STRUCTURE
GND
GND
Figure 2. LOUT/OUT Pins Internal Input/Output Schematic
Figure 3. SEL Pin Internal Input/Output Schematic
V
CC
ESD
STRUCTURE
300Ω
IN-
(L)IN-
75Ω
75Ω
43Ω
IN+
OUT+
43Ω
IN+
OUT+
(L)IN+
MAX3750
MAX3751
OUT-
300Ω
176Ω
43Ω
IN-
MAX3750
MAX3751
OUT-
176Ω
43Ω
GND
Figure 4. LIN/IN Pins Internal Input/Output Schematic
Figure 5. 50Ω Termination Applications
_______________________________________________________________________________________
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