Si53320-28 Data Sheet
Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECL
Outputs from Any-Format Input and Wide Frequency Range from
DC up to 1250 MHz
The Si53320–28 family of LVPECL fanout buffers is ideal for clock/data distribution and
redundant clocking applications. These devices feature typical ultra-low jitter character-
istics of 50 fs and operate over a wide frequency range from dc to 725/1250 MHz. Built-
in LDOs deliver high PSRR performance and reduce the need for external components,
simplifying low-jitter clock distribution in noisy environments.
The Si53320–28 family is available in multiple configurations, with some versions offer-
ing a selectable input clock using a 2:1 input mux. Other features include independent
output enable and built-in format translation. These buffers can be paired with the
Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
KEY FEATURES
• Ultra-low additive jitter: 50 fs rms
• Built-in LDOs for high PSRR performance
• Up to 10 LVPECL Outputs
• Any-format Inputs (LVPECL, Low-power
LVPECL, LVDS, CML, HCSL, LVCMOS)
• Wide frequency range: dc to 1250 MHz
• Output Enable option
• Multiple configuration options
• Dual Bank option
• 2:1 Input Mux operation
• RoHS compliant, Pb-free
• Temperature range: –40 to +85 °C
VDD
Power Supply Filtering
VDD
4
4 Outputs
OEb
5
5 Outputs
Si53320
Si53323
CLK
Power Supply Filtering
2
2 Outputs
Si53322
CLK0*
0
VDDOA
CLK1*
CLK_SEL
1
3
3
OEAb
3 Outputs
Si53327/28
3 Outputs
OEBb
VDDOB
VDD
Power Supply Filtering
CLK0
Si53321/26
5
5 Outputs
Si53325
5 Outputs
10
10 Outputs
CLK1
5
*Si53326/28 require Single-ended Inputs
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Rev. 1.2
Si53320-28 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si5332x Ordering Guide
Part Number
Si53320-B-GT
Si53321-B-GM
Si53321-B-GQ
Si53322-B-GM
Input
2:1 selectable MUX
Any-format
2:1 selectable MUX
Any-format
2:1 selectable MUX
Any-format
1 bank / 1 Input
Any-format
2:1 selectable MUX
Any-format
2 banks / 2 Inputs
Any-format
2 banks / 2 Inputs
Any-format
2:1 selectable MUX
LVCMOS
2:1 selectable MUX
Any-format
2:1 selectable MUX
LVCMOS
LVPECL Output
1 bank / 5 Outputs
1 bank / 10 Outputs
1 bank / 10 Outputs
1 bank / 2 Outputs
1 bank / 4 Outputs
2 banks / 5 Outputs
2 banks / 5 Outputs
1 bank / 10 Outputs
2 banks / 3 Outputs
2 banks / 3 Outputs
Output Enable
Single
—
—
—
—
—
—
—
1 per bank
1 per bank
Frequency Range
dc to 725 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 1250 MHz
dc to 200 MHz
dc to 1250 MHz
dc to 200 MHz
Package
20-TSSOP
32-QFN
5 x 5 mm
32-eLQFP
7 x 7 mm
16-QFN
3 x 3 mm
16-QFN
3 x 3 mm
32-QFN
5 x 5 mm
32-eLQFP
7 x 7 mm
32-QFN
5 x 5 mm
24-QFN
4 x 4 mm
24-QFN
4 x 4 mm
Si53323-B-GM
Si53325-B-GM
Si53325-B-GQ
Si53326-B-GM
Si53327-B-GM
Si53328-B-GM
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Rev. 1.2 | 1
Si53320-28 Data Sheet
Functional Description
2. Functional Description
The Si53320-28 are a family of low-jitter, low-skew, fixed-format (LVPECL) buffers. All devices except the Si53326 and Si53328 have a
universal input that accepts most common differential or LVCMOS input signals. The Si53326 and Si53328 accept only single-ended
LVCMOS inputs. These devices are available in multiple configurations customized for the end application (refer to
1. Ordering Guide
for more details on configurations).
2.1 Universal, Any-Format Input Termination (Si53320/21/22/23/25/27)
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-power LVPECL,
LVCMOS, LVDS, HCSL, and CML. The tables below summarize the various ac- and dc-coupling options supported by the device. For
the best high-speed performance, the use of differential formats is recommended. For both single-ended and differential input clocks,
the fastest possible slew rate is recommended since low slew rates can increase the noise floor and degrade jitter performance.
Though not required, a minimum slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats.
See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance”
for more information.
Table 2.1. Clock Input Options
Clock Format
AC-Coupled
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
DC-Coupled
LVPECL/Low-power LVPECL
LVCMOS
LVDS
HCSL
CML
N/A
No
No
No
No
Yes
Yes
Yes
Yes (3.3 V)
No
N/A
No
Yes
No
Yes
Yes
Yes
Yes
Yes (3.3 V)
Yes
1.8 V
2.5/3.3 V
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Si53320-28 Data Sheet
Functional Description
V
DD
0.1 µF
CLKx
100
CLKxb
Si53320/21/22/23/25/27
0.1 µF
Figure 2.1. Differential (HCSL, LVPECL, Low-Power LVPECL, LVDS, CML) AC-Coupled Input Termination
V
DD
DC-Coupled
V
DD
= 3.3 V or 2.5 V
CMOS
Driver
50
Rs
1k
V
DD
Si53320/21/22/23/25/27
CLKx
CLKxb
V
TERM
= V
DD
/2
1k
V
DD
V
DD
AC-Coupled
V
DD
= 3.3 V or 2.5 V
CMOS
Driver
1k
1k
V
DD
Si53320/21/22/23/25/27
CLKx
V
BIAS
= V
DD
/2
50
Rs
1k
CLKxb
Note:
Value for Rs should be chosen so that the total
source impedance matches the characteristic
impedance of the PCB trace.
1k
V
TERM
= V
DD
/2
Figure 2.2. Single-Ended (LVCMOS) Input Termination
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Si53320-28 Data Sheet
Functional Description
V
DD
DC Coupled LVPECL Input Termination Scheme 1
R
1
V
DD
= 3.3 V or 2.5 V
“Standard”
LVPECL
Driver
50
50
R
2
3.3 V LVPECL:
R
1
= 127 Ohm, R
2
= 82.5 Ohm
2.5 V LVPECL:
R
1
= 250 Ohm, R
2
= 62.5 Ohm
R
2
CLKx
CLKxb
R
1
V
DD
Si53320/21/22/23/25/27
V
TERM
= V
DD
– 2V
R
1
// R
2
= 50 Ohm
DC Coupled LVPECL Input Termination Scheme 2
V
DD
= 3.3 V or 2.5 V
“Standard”
LVPECL
Driver
50
50
50
50
CLKx
CLKxb
V
DD
Si53320/21/22/23/25/27
V
TERM
= V
DD
– 2 V
DC Coupled LVDS Input Termination
V
DD
= 3.3 V or 2.5 V
Standard
LVDS
Driver
50
100
50
CLKx
CLKxb
V
DD
Si53320/21/22/23/25/27
DC Coupled HCSL Input Termination Scheme
V
DD
= 3.3 V
Standard
HCSL Driver
33
50
33
50
50
50
CLKx
CLKxb
V
DD
Si53320/21/22/23/25/27
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 2.3. Differential DC-Coupled Input Terminations (Si53320/21/22/23/25/27)
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