FM31L276/FM31L278
64-Kbit/256-Kbit Integrated Processor
Companion with F-RAM
256-Kbit (32 K × 8) Serial (SPI) F-RAM
Features
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Restriction of hazardous substances (RoHS) compliant
Underwriters laboratory (UL) recognized
64-Kbit/256-Kbit ferroelectric random access memory (F-RAM)
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Logically organized as 8 K × 8 (FM31L276) / 32 K × 8
(FM31L278)
14
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High-endurance 100 trillion (10 ) read/writes
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151-year data retention (See the
Data Retention and
Endurance
table)
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NoDelay™ writes
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Advanced high-reliability ferroelectric process
High Integration Device Replaces Multiple Parts
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Serial nonvolatile memory
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Real time clock (RTC)
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Low voltage reset
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Watchdog timer
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Early power-fail warning/NMI
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Two 16-bit event counter
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Serial number with write-lock for security
Real-time Clock/Calendar
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Backup current at 2 V: 1.15
A
at +25
C
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Seconds through centuries in BCD format
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Tracks leap years through 2099
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Uses standard 32.768 kHz crystal (6 pF/12.5 pF)
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Software calibration
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Supports battery or capacitor backup
Processor Companion
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Active-low reset output for V
DD
and watchdog
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Programmable low-V
DD
reset trip point
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Manual reset filtered and debounced
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Programmable watchdog timer
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Dual Battery-backed event counter tracks system intrusions
or other events
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Comparator for power-fail interrupt
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64-bit programmable serial number with lock
Fast 2-wire serial interface (I
2
C)
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Up to 1-MHz frequency
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Supports legacy timings for 100 kHz and 400 kHz
2
❐
RTC, Supervisor controlled via I C interface
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Device select pins for up to 4 memory devices
Low power consumption
❐
1.5 mA active current at 1 MHz
❐
120
A
standby current
Operating voltage: V
DD
= 2.7 V to 3.6 V
Industrial temperature: –40
C
to +85
C
14-pin small outline integrated circuit (SOIC) package
Functional Overview
The FM31L276/FM31L278 device integrates F-RAM memory
with the most commonly needed functions for processor-based
systems. Major features include nonvolatile memory, real time
clock, low-V
DD
reset, watchdog timer, nonvolatile event counter,
lockable 64-bit serial number area, and general purpose
comparator that can be used for a power-fail (NMI) interrupt or
any other purpose.
The FM31L276/FM31L278 is a 64-Kbit/256-Kbit nonvolatile
memory employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is nonvolatile
and performs reads and writes similar to a RAM. This memory is
truly nonvolatile rather than battery backed. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by other
nonvolatile memories. The FM31L276/FM31L278 is capable of
supporting 10
14
read/write cycles, or 100 million times more write
cycles than EEPROM.
The real time clock (RTC) provides time and date information in
BCD format. It can be permanently powered from an external
backup voltage source, either a battery or a capacitor. The
timekeeper uses a common external 32.768 kHz crystal and
provides a calibration mode that allows software adjustment of
timekeeping accuracy.
The processor companion includes commonly needed CPU
support functions. Supervisory functions include a reset output
signal controlled by either a low V
DD
condition or a watchdog
timeout. RST goes active when V
DD
drops below a
programmable threshold and remains active for 100 ms after
V
DD
rises above the trip point. A programmable watchdog timer
runs from 100 ms to 3 seconds. The watchdog timer is optional,
but if enabled it will assert the reset signal for 100 ms if not
restarted by the host before the timeout. A flag-bit indicates the
source of the reset.
A comparator on PFI compares an external input pin to the
onboard 1.2 V reference. This is useful for generating a
power-fail interrupt (NMI) but can be used for any purpose. The
family also includes a programmable 64-bit serial number that
can be locked making it unalterable. Additionally it offers a dual
battery-backed event counter that tracks the number of rising or
falling edges detected on a dedicated input pin.
For a complete list of related documentation, click
here.
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Cypress Semiconductor Corporation
Document Number: 001-86392 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 5, 2014
FM31L276/FM31L278
Logic Block Diagram
Document Number: 001-86392 Rev. *B
Page 2 of 33
FM31L276/FM31L278
Contents
Pinout ................................................................................ 4
Pin Definitions .................................................................. 4
Overview............................................................................ 5
Memory Architecture ................................................... 5
Processor Companion ..................................................... 5
Processor Supervisor .................................................. 5
Manual Reset .............................................................. 6
Reset Flags ................................................................. 6
Early Power Fail Comparator ...................................... 6
Event Counter ............................................................. 7
Serial Number ............................................................. 7
Real-time Clock Operation............................................... 7
Backup Power ............................................................. 8
Trickle Charger............................................................ 8
Calibration ................................................................... 9
Crystal Oscillator ......................................................... 9
Layout Recommendations............................................. 10
Register Map ................................................................... 13
I2C Interface .................................................................... 19
STOP Condition (P)................................................... 19
START Condition (S)................................................. 19
Data/Address Transfer .............................................. 19
Acknowledge / No-acknowledge ............................... 19
Slave Address ........................................................... 20
Addressing Overview - Memory ................................ 20
Addressing Overview - RTC & Companion ............... 20
Data Transfer ............................................................ 20
Memory Operation.......................................................... 21
Memory Write Operation ........................................... 21
Memory Read Operation ........................................... 21
RTC/Companion Write Operation ............................. 23
RTC/Companion Read Operation ............................. 23
Addressing FRAM Array in the FM31L276/FM31L278
Family........................................................................ 23
Maximum Ratings........................................................... 24
Operating Range............................................................. 24
DC Electrical Characteristics ........................................ 24
Data Retention and Endurance ..................................... 26
Capacitance .................................................................... 26
Thermal Resistance........................................................ 26
AC Test Loads and Waveforms..................................... 26
AC Test Conditions ................................................... 26
Supervisor Timing .......................................................... 27
AC Switching Characteristics ....................................... 28
Ordering Information...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagram............................................................ 30
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support....................... 33
Products .................................................................... 33
PSoC® Solutions ...................................................... 33
Cypress Developer Community................................. 33
Technical Support ..................................................... 33
Document Number: 001-86392 Rev. *B
Page 3 of 33
FM31L276/FM31L278
Pinout
Figure 1. 14-pin SOIC pinout
CNT1
CNT2
A0
A1
CAL/PFO
RST
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
SCL
SDA
X2
X1
PFI
V
BAK
Pin Definitions
Pin Name
A1-A0
I/O Type
Input
Description
Device Select Address 1-0.
These pins are used to select one of up to 4 devices of the same type
on the same I
2
C bus. To select the device, the address value on the three pins must match the
corresponding bits contained in the slave address. The address pins are pulled down internally.
SDA
Input/Output
Serial Data/Address.
This is a bi-directional pin for the I
2
C interface. It is open-drain and is intended
to be wire-OR'd with other devices on the I
2
C bus. The input buffer incorporates a Schmitt trigger for
noise immunity and the output driver includes slope control for falling edges. An external pull-up
resistor is required.
Input
Serial Clock.
The serial clock pin for the I
2
C interface. Data is clocked out of the device on the falling
edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input
for noise immunity.
Event Counter Inputs.
These battery-backed inputs increment counters when an edge is detected
on the corresponding CNT pin. The polarity is programmable. These pins should not be left floating.
Tie to ground if these pins are not used.
SCL
CNT1, CNT2
Input
X1, X2
RST
PFI
CAL/PFO
V
BAK
Input/Output 32.768 kHz crystal connection. When using an external oscillator, apply the clock to X1 and a DC
mid-level to X2. These pins should be left unconnected if RTC is not used.
Input/Output
Reset.
This active-low output is open drain with weak pull-up. It is also an input when used as a manual
reset. This pin should be left floating if unused.
Input
Output
Early Power-fail Input.
Typically connected to an unregulated power supply to detect an early power
failure. This pin must be tied to ground if unused.
Calibration/Early Power-fail Output.
In calibration mode, this pin supplies a 512 Hz square-wave
output for clock calibration. In normal operation, this is the early power-fail output.
Power supply
Backup supply voltage.
Connected to a 3 V battery or a large value capacitor. If no backup supply
is used, this pin should be tied to ground and the VBC bit should be cleared in the RTC register 0Bh.
The trickle charger is UL recognized and ensures no excessive current when using a lithium battery.
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
V
SS
V
DD
Document Number: 001-86392 Rev. *B
Page 4 of 33
FM31L276/FM31L278
Overview
The FM31L276/FM31L278 device combines a serial nonvolatile
RAM with a real time clock (RTC) and a processor companion.
The companion is a highly integrated peripheral including a
processor supervisor, a comparator used for early power-fail
warning, nonvolatile event counters, and a 64-bit serial number.
The FM31L276/FM31L278 integrates these complementary but
distinct functions under a common interface in a single package.
The product is organized as two logical devices. The first is a
memory and the second is the companion which includes all the
remaining functions. From the system perspective they appear
to be two separate devices with unique IDs on the serial bus.
The memory is organized as a standalone nonvolatile I
2
C
memory using standard device ID value. The real time clock and
supervisor functions are accessed with a separate I
2
C device ID.
This allows clock/calendar data to be read while maintaining the
most recently used memory address. The clock and supervisor
functions are controlled by 25 special function registers. The
RTC and event counter circuits are maintained by the power
source on the V
BAK
pin, allowing them to operate from battery or
backup capacitor power when V
DD
drops below a set threshold.
Each functional block is described below.
Processor Companion
In addition to nonvolatile RAM, the FM31L276/FM31L278
incorporates a real time clock and highly integrated processor
companion. The companion includes a low-V
DD
reset, a
programmable watchdog timer, a battery-backed event
counters, a comparator for early power-fail detection or other
purposes, and a 64-bit serial number.
Processor Supervisor
Supervisors provide a host processor two basic functions:
detection of power supply fault conditions and a watchdog timer
to
escape
a
software
lockup
condition.
The
FM31L276/FM31L278 has a reset pin (RST) to drive a processor
reset input during power faults, power-up, and software lockups.
It is an open drain output with a weak internal pull-up to V
DD
. This
allows other reset sources to be wire-OR'd to the RST pin. When
V
DD
is above the programmed trip point, RST output is pulled
weakly to V
DD
. If V
DD
drops below the reset trip point voltage
level (V
TP
), the RST pin will be driven LOW. It will remain LOW
until V
DD
falls too low for circuit operation which is the V
RST
level.
When V
DD
rises again above V
TP
, RST continues to drive LOW
for at least 100 ms (t
RPU
) to ensure a robust system reset at a
reliable V
DD
level. After t
RPU
has been met, the RST pin will
return to the weak HIGH state. While RST is asserted, serial bus
activity is locked out even if a transaction occurred as V
DD
dropped below V
TP
. A memory operation started while V
DD
is
above V
TP
will be completed internally.
Table 1
below shows how bit VTP controls the trip point of the
low-V
DD
reset. They are located in register 0Bh, bits 1 and 0. The
reset pin will drive LOW when V
DD
is below the selected V
TP
voltage, and the I
2
C interface and F-RAM array will be locked
out. Note that the bit 1 location is a don't care.
Figure 2
illustrates
the reset operation in response to a low V
DD
.
Table 2. VTP setting
VTP Setting
2.6 V
2.9 V
Figure 2. Low V
DD
Reset
VTP
0
1
Memory Architecture
The FM31L276/FM31L278 device is available in memory size
64-Kbit/256-Kbit. The device uses two-byte addressing for the
memory portion of the chip. This makes the device software
compatible with its standalone memory counterparts, but makes
them compatible within the entire family.
The memory array is logically organized as 8,192 × 8 bits /
32,768 × 8 bits and is accessed using an industry-standard I
2
C
interface. The memory is based on F-RAM technology.
Therefore it can be treated as RAM and is read or written at the
speed of the I
2
C bus with no delays for write operations. It also
offers effectively unlimited write endurance unlike other
nonvolatile memory technologies. The I
2
C protocol is described
on
page 19.
The memory array can be write-protected by software. Two bits
in the processor companion area (WP1, WP0 in register 0Bh)
control the protection setting. Based on the setting, the protected
addresses cannot be written and the I
2
C interface will not
acknowledge any data to protected addresses. The special
function registers containing these bits are described in detail
below.
Table 1. Block Memory Write Protection
WP1
0
0
1
1
WP0
0
1
0
1
Protected Address Range
None
Bottom 1/4
Bottom 1/2
Full array
V
DD
V
TP
t
RPU
RST
A watchdog timer can also be used to drive an active reset signal.
The watchdog is a free-running programmable timer. The
timeout period can be software programmed from 100 ms to 3
seconds in 100 ms increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary with
Page 5 of 33
Document Number: 001-86392 Rev. *B
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