Product Specification
PE4242
Product Description
The PE4242 UltraCMOS™ RF Switch is designed to cover a
broad range of applications from 10 MHz through 3 GHz. This
reflective switch integrates on-board CMOS control logic with a
low voltage CMOS-compatible control interface, and can be
controlled using either single-pin or complementary control
inputs. Using a nominal +3-volt power supply voltage, a typical
input 1 dB compression point of +27 dBm can be achieved.
The PE4242 RF Switch is manufactured on Peregrine’s
UltraCMOS™ process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
Figure 1. Functional Diagram
SPDT UltraCMOS™
10 MHz - 3 GHz RF Switch
Features
Single-pin or complementary CMOS
logic control inputs
+3.0-volt power supply needed for single
-pin control mode
Low insertion loss: 0.7 dB at 1000 MHz,
0.9 dB at 2000 MHz
Isolation of 32 dB at 1000 MHz, 23 dB at
2000 MHz
Typical input 1 dB compression point of
+27 dBm
Ultra-small SC-70 package
le
Parameter
Operation Frequency
1
Insertion Loss
Isolation
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Video Feedthrough
2
Input 1 dB Compression
Input IP3
2000 MHz
2000 MHz, 14 dBm input power
26
43
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
50% CTRL to 0.1 dB of final value, 1 GHz
50% CTRL to 25 dB isolation, 1 GHz
30
21
18
16
te
bs
o
71-0015
Figure 2. Package Type
6-lead SC-70
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V (Z
S
= Z
L
= 50
Ω)
Conditions
Minimum
10
0.7
0.9
32
23
22
18
300
200
15
27
45
Typical
Maximum
3000
0.85
1.05
Units
MHz
dB
dB
dB
dB
dB
dB
ns
ns
mV
pp
dBm
dBm
Notes: 1. Device linearity will begin to degrade below 10 MHz
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50
Ω
test set-up, measured with
1ns risetime pulses and 500 MHz bandwidth.
O
Document No. 70-0095-04
│
www.psemi.com
©2003-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4242
Product Specification
Figure 3. Pin Configuration (Top View)
Exceeding absolute maximum ratings may cause
permanent damage. Operation between operating
range maximum and absolute maximum for
extended periods may reduce reliability.
Table 4. DC Electrical Specifications
Parameter
Min
2.7
Typ
3.0
250
0.7x V
DD
0.3x V
DD
Max
3.3
500
Units
V
nA
V
V
V
DD
Power Supply Voltage
Table 2. Pin Descriptions
1
Pin No.
1
2
3
4
5
Pin Name
RF1
GND
RF2
CTRL
RFC
RF1 port
2
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF2 port
1
Switch control input, CMOS logic level
Common RF port for switch
1
This pin supports two interface options:
Single-pin control mode.
A nominal 3-volt
supply connection is required.
Complementary-pin control mode.
A
complementary CMOS control signal
to CTRL is supplied to this pin.
Bypassing on this pin is not required in
this mode.
Description
I
DD
Power Supply Current
(V
DD
= 3 V, V
CTRL
= 3 V)
Control Voltage High
Control Voltage Low
6
CTRL
or
V
DD
Note: 1. Operation should be restricted to the limits in the Operating Ranges table
2. All RF pins must be DC blocked with an external series capacitor or held
at 0 V
DC
.
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
V
ESD1
Parameter/Conditions
Power supply voltage
Voltage on any input
O
Min
-0.3
-0.3
-65
-40
Table 3. Absolute Maximum Ratings
Storage temperature range
Operating temperature range
Input power (50
Ω)
HBM ESD Voltage
Note: 1. Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7)
©2003-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 9
bs
o
Max
4.0
Units
V
V
°C
°C
dBm
V
V
DD
+ 0.3
150
85
30
1500
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
le
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE4242 in the 6-lead SC-70 package is MSL1.
te
Document No. 70-0095-04
│
UltraCMOS™ RFIC Solutions
PE4242
Product Specification
Table 5. Single-pin Control Logic Truth Table
Control Voltages
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = Low
Pin 6 (V
DD
) = V
DD
Pin 4 (CTRL) = High
Signal Path
RFC to RF1
RFC to RF2
Control Logic Input
The PE4242 is a versatile RF CMOS switch that
supports two operating control modes; single-pin
control mode and complementary-pin control
mode.
Single-pin control mode
enables the switch to
operate with a single control pin (pin 4) supporting
a +3-volt CMOS logic input, and requires a
dedicated +3-volt power supply connection on
pin 6 (V
DD
). This mode of operation reduces the
number of control lines required and simplifies the
switch control interface typically derived from a
CMOS
μProcessor
I/O port.
Complementary-pin control mode
allows the
switch to operate using complementary control
pins CTRL and
CTRL
(pins 4 & 6), that can be
directly driven by +3-volt CMOS logic or a suitable
μProcessor
I/O port. This enables the PE4242 to
be used as a potential alternate source for SPDT
RF switch products used in positive control
voltage mode and operating within the PE4242
operating limits.
Table 6. Complementary-pin Control Logic
Truth Table
Control Voltages
Pin 6 (CTRL or V
DD
) = High
Pin 4 (CTRL) = Low
Pin 6 (CTRL or V
DD
) = Low
Pin 4 (CTRL) = High
Signal Path
RFC to RF1
RFC to RF2
Document No. 70-0095-04
│
www.psemi.com
O
©2003-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
bs
o
le
te
PE4242
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4242 SPDT switch. The RF common port is
connected through a 50
Ω
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
Ω
transmission lines to the
top two SMA connectors on the right side of the
board, J3 and J2, respectively. A through
transmission line connects SMA connectors J4
and J5. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.0476”, trace
gaps of 0.030”, dielectric thickness of 0.028”,
metal thickness of 0.0021” and
ε
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J6-3) is connected
to the device V1 or CTRL input. The fourth pin to
the right (J6-7) is connected to the device V2 or
CTRL/V
DD
input.
Figure 4. Evaluation Board Layout
bs
o
le
101/0083
O
Figure 5. Evaluation Board Schematic
te
102/0145
©2003-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 9
Document No. 70-0095-04
│
UltraCMOS™ RFIC Solutions
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
PE4242
Product Specification
Typical Performance Data @ -40 °C to 85 °C (Unless otherwise noted)
Figure 6. Insertion Loss – RFC to RF1
Figure 7. Input 1 dB Compression Point & IIP3
(Typical Performance @ 25 °C)
0
60
60
-0.3
-40°C
Insertion Loss (dB)
50
50
1dB Compression Point (dBm)
IIP3 (dBm)
-0.6
40
40
-0.9
85°C
25°C
30
30
-1.5
0
500
1000
1500
Frequency (MHz)
2000
2500
3000
te
20
-1.2
le
0
-20
Isolation (dB)
-40
-60
-80
-100
0
0
500
1000
1500
2000
2500
20
3000
Frequency (MHz)
Figure 8. Insertion Loss – RFC to RF2
bs
o
Figure 9. Isolation – RFC to RF1
(Typical Performance @ 25 °C)
0
-0.3
-40°C
Insertion Loss (dB)
-0.6
-0.9
85°C
25°C
-1.2
-1.5
0
500
1000
1500
Frequency (MHz)
2000
2500
3000
O
500
1000
1500
Frequency (MHz)
2000
2500
3000
Document No. 70-0095-04
│
www.psemi.com
©2003-2011 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
