Si52143
PCI-E
XPRESS
G
EN
1, G
EN
2, & G
EN
3 Q
UAD
O
UTPUT
C
L O C K
G
ENERATOR WITH
2 5 M H
Z
R
E F E R E N C E
C
L O C K
Features
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Gen 3 SRNS Compliant
Supports Serial ATA (SATA) at
100 MHz
Low power, push-pull HCSL
compatible differential outputs
No termination resistors required
Dedicated output enable hardware
pins for each clock output
Spread enable pin on differential
clocks
Four PCI-Express clocks
25 MHz reference clock output
25 MHz crystal input or clock input
Signal integrity tuning
I
2
C support with readback
capabilities
Triangular spread spectrum profile
for maximum electromagnetic
interference (EMI) reduction
Industrial temperature
–40 to 85 °C
3.3 V power supply
24-pin QFN package
Ordering Information:
See page 18
Applications
Pin Assignments
VSS_CORE
XIN/CLKIN
VDD_CORE
SDATA
20
Network attached storage
Multi-function printer
Wireless access point
Routers
Description
VDD_REF
1
2
3
4
5
6
XOUT
24
23
22
21
SCLK
19
1
18 OE[3:2]
The Si52143 is a spread-spectrum enabled PCIe clock generator that can source
four PCIe clocks and a 25 MHz reference clock. The device has three hardware
output enable pins for enabling the outputs (on the fly while powered on), and one
hardware pin to control spread spectrum on PCIe clock outputs. In addition to the
hardware control pins, I2C programmability is also available to dynamically control
skew, edge rate and amplitude on the true, compliment, or both differential signals
on the PCIe clock outputs. This control feature enables optimal signal integrity as
well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for
signal integrity tuning and configurability. Measuring PCIe clock jitter is quick and
easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
REF
SSON
2
17 VDD_DIFF
16 DIFF3
15 DIFF3
14 DIFF2
13 DIFF2
7
8
9
10
11
12
VSS_REF
OE_REF
1
VDD_DIFF
25
GND
DIFF0
DIFF1
DIFF1
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Functional Block Diagram
Patents pending
XIN/CLKIN
XOUT
REF
DIFF0
DIFF1
PLL
(SSC)
Divider
DIFF2
DIFF3
SCLK
SDATA
OE_REF
OE [1:0]
OE [3:2]
SSON
Control
RAM
Control & Memory
Rev 1.4 4/16
Copyright © 2016 by Silicon Laboratories
VDD_DIFF
OE[1:0]
1
DIFF0
Si52143
Si52143
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. SSON Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Rev 1.4
3
Si52143
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
3.3 V Output High Voltage
(Single-Ended Outputs)
3.3 V Output High Voltage
(Single-Ended Outputs)
High-impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Dynamic Supply Current
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
V
OH
V
OL
I
OZ
C
IN
C
OUT
L
IN
I
DD_3.3V
All outputs enabled. Differ-
ential clocks with 5” traces
and 2 pF load.
Test Condition
3.3 ± 5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up resis-
tors, 0 < V
IN
< V
DD
I
OH
= –1 mA
I
OL
= 1 mA
Min
3.135
2.0
V
SS
–
0.3
2.2
—
—
–5
2.4
–
–10
1.5
—
—
—
Typ
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
—
0.4
10
5
6
7
55
Unit
V
V
V
V
V
A
A
V
V
µA
pF
pF
nH
mA
4
Rev 1.4
Si52143
Table 2. AC Electrical Specification
Parameter
Crystal
Long-term Accuracy
Clock Input
Duty Cycle
CLKIN Rising and Falling Slew
Rate
Cycle to Cycle Jitter
Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
Duty Cycle
Output-to-Output Skew
Cycle to Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Separate Reference No
Spread, SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
Long Term Accuracy
Rising/Falling Slew Rate
Voltage High
Voltage Low
Crossing Point Voltage at 0.7 V
Swing
T
DC
T
SKEW
T
CCJ
Pk-Pk
RMS
GEN2
RMS
GEN3
RMS
GEN3_SRNS
Measured at 0 V differential
Measured at 0 V differential
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz< F < Nyquist Rate
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
Measured at 0 V differential
Measured differentially from
±150 mV
45
—
—
0
0
0
0
—
—
—
35
40
2
2
0.5
0.35
55
50
50
50
2.6
2.6
0.9
0.64
%
ps
ps
ps
ps
ps
ps
ps
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
Measured at VDD/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
45
0.5
—
—
2
—
—
–35
—
—
—
—
—
—
—
—
55
4.0
250
350
VDD+0.3
0.8
35
—
%
V/ns
ps
ps
V
V
µA
µA
L
ACC
Measured at VDD/2 differential
—
—
250
ppm
Symbol
Test Condition
Min
Typ
Max
Unit
RMS
GEN4
L
ACC
T
R
/ T
F
V
HIGH
V
LOW
V
OX
—
—
1
—
–0.3
300
0.5
—
—
—
—
—
0.9
100
8
1.15
—
550
ps
ppm
V/ns
V
V
mV
Notes:
1.
Visit
www.pcisig.com
for complete PCIe specifications.
2.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
Rev 1.4
5
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