HUF75321P3, HUF75321S3S
Data Sheet
December 2001
35A, 55V, 0.034 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
innovative UltraFET® process. This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstanding performance. This device is capable
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portable
and battery-operated products.
Formerly developmental type TA75321.
Features
• 35A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Models
- Thermal Impedance SPICE and SABER Models
Available on the WEB at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
Ordering Information
PART NUMBER
HUF75321P3
HUF75321S3S
PACKAGE
TO-220AB
TO-263AB
BRAND
75321P
75321S
S
G
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75321S3ST.
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-263AB
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
55
55
±20
35
Figure 4
Figures 6, 14, 15
93
0.625
-55 to 175
300
260
UNITS
V
V
V
A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . T
pkg
W
W/
o
C
o
C
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 150
o
C.
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 50V, V
GS
= 0V
V
DS
= 45V, V
GS
= 0V, T
C
= 150
o
C
55
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Reverse Transfer Capacitance
I
GSS
V
GS
=
±20V
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 35A, V
GS
= 10V (Figure 9)
2
-
-
0.028
4
0.034
V
Ω
R
θJC
R
θJA
(Figure 3)
TO-220, TO-263
-
-
-
-
1.6
62
o
C/W
o
C/W
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 30V, I
D
≅
35A,
R
L
= 0.86Ω, V
GS
=
10V,
R
GS
= 25Ω
-
-
-
-
-
-
-
11
55
47
66
-
100
-
-
-
-
170
ns
ns
ns
ns
ns
ns
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 30V,
I
D
≅
35A,
R
L
= 0.86Ω
I
g(REF)
= 1.0mA
(Figure 13)
-
-
-
-
-
36
21
1.3
3
9
44
26
1.6
-
-
nC
nC
nC
nC
nC
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Electrical Specifications
PARAMETER
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
680
270
60
-
-
-
pF
pF
pF
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
SYMBOL
V
SD
t
rr
Q
RR
I
SD
= 35A
I
SD
= 35A, dI
SD
/dt = 100A/µs
I
SD
= 35A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
TYP
-
-
-
MAX
1.25
59
82
UNITS
V
ns
nC
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
I
D
, DRAIN CURRENT (A)
30
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
0
40
20
10
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
10
-1
10
0
10
1
SINGLE PULSE
0.01
-5
10
10
-4
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Typical Performance Curves
500
(Continued)
T
C
= 25
o
C
I
DM
, PEAK CURRENT (A)
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
175 - T
C
150
100
V
GS
= 20V
V
GS
= 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
300
I
AS
, AVALANCHE CURRENT (A)
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
300
I
D
, DRAIN CURRENT (A)
100
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
≠
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
100
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
V
DSS(MAX)
= 55V
1
1
10
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
100
200
1ms
10ms
10
0.001
0.1
0.01
t
AV
, TIME IN AVALANCHE (ms)
1
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
75
V
GS
= 20V
V
GS
= 10V
V
GS
= 8V
V
GS
= 7V
V
GS
= 6V
45
75
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
60
175
o
C
45
-55
o
C
I
D
, DRAIN CURRENT (A)
60
30
V
GS
= 5V
15
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1.5
3.0
4.5
6.0
7.5
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
30
15
25
o
C
0
0
V
DD
= 15V
7.5
0
1.5
3.0
4.5
6.0
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
HUF75321P3, HUF75321S3S
Typical Performance Curves
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
GS
= 10V, I
D
= 35A
NORMALIZED GATE
THRESHOLD VOLTAGE
(Continued)
1.2
V
GS
= V
DS
, I
D
= 250µA
2.0
1.0
1.5
0.8
1.0
0.5
-80
-40
0
40
80
120
160
200
0.6
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
I
D
= 250µA
1000
V
GS
= 0V, f = 1MHz
C
ISS
= C
GS
+ C
GD
C
RSS
= C
GD
C
OSS
≈
C
DS
+ C
GD
C, CAPACITANCE (pF)
800
C
ISS
600
1.1
400
C
OSS
200
C
RSS
1.0
0.9
-80
-40
0
40
80
120
160
200
0
0
10
20
30
40
50
60
T
J
, JUNCTION TEMPERATURE (
o
C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
V
GS
, GATE TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
I
D
= 35A
I
D
= 17.5A
I
D
= 8.75A
15
20
25
2
V
DD
= 30V
0
0
5
10
Q
g
, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75321P3, HUF75321S3S Rev. B
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