PSMN013-80YS
N-channel LFPAK 80 V 12.9 mΩ standard level MOSFET
Rev. 01 — 25 June 2009
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
Advanced TrenchMOS provides low
RDSon and low gate charge
High efficiency gains in switching
power converters
Improved mechanical and thermal
characteristics
LFPAK provides maximum power
density in a Power SO8 package
1.3 Applications
DC-to-DC converters
Lithium-ion battery protection
Load switching
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
T
j
Quick reference
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
-55
-
Typ
-
-
-
-
-
Max
80
60
106
175
70
Unit
V
A
W
°C
mJ
drain-source voltage
drain current
total power dissipation
junction temperature
Symbol Parameter
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 55 A; V
sup
≤
80 V;
avalanche energy
R
GS
= 50
Ω;
unclamped
Dynamic characteristics
Q
GD
Q
G(tot)
gate-drain charge
total gate charge
V
GS
= 10 V; I
D
= 25 A; V
DS
= 40 V; see
Figure 14;
see
Figure 15
V
GS
= 10 V; I
D
= 25 A; V
DS
= 40 V; see
Figure 14;
see
Figure 15
V
GS
= 10 V; I
D
= 15 A; T
j
= 100 °C; see
Figure 12
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C; see
Figure 13
-
-
8
37
-
-
nC
nC
Static characteristics
R
DSon
drain-source on-state
resistance
-
-
-
9.7
19.8
12.9
mΩ
mΩ
NXP Semiconductors
PSMN013-80YS
N-channel LFPAK 80 V 12.9 mΩ standard level MOSFET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669
(LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN013-80YS
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
T
sld(M)
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak soldering
temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
Max
80
80
20
42
60
233
106
175
175
260
Unit
V
V
V
A
A
A
W
°C
°C
°C
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
I
S
I
SM
E
DS(AL)S
-
-
-
60
233
70
A
A
mJ
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 55 A; V
sup
≤
80 V;
drain-source avalanche R
GS
= 50
Ω;
unclamped
energy
PSMN013-80YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
2 of 13
NXP Semiconductors
PSMN013-80YS
N-channel LFPAK 80 V 12.9 mΩ standard level MOSFET
60
I
D
(A)
003aad230
120
P
der
(%)
80
03aa16
40
20
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aad314
10
3
I
D
(A)
10
2
100μ s
10
Limit R
DSon
= V
DS
/ I
D
10μ s
1
DC
1ms
10ms
100ms
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN013-80YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
3 of 13
NXP Semiconductors
PSMN013-80YS
N-channel LFPAK 80 V 12.9 mΩ standard level MOSFET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
0.54
Max
1.4
Unit
K/W
thermal resistance from see
Figure 4
junction to mounting
base
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
-1
0.1
0.05
0.02
10
-2
single shot
t
p
P
003aac657
δ
=
t
p
T
t
T
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN013-80YS_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
4 of 13
NXP Semiconductors
PSMN013-80YS
N-channel LFPAK 80 V 12.9 mΩ standard level MOSFET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C; see
Figure 10;
see
Figure 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C; see
Figure 10;
see
Figure 11
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C; see
Figure 10;
see
Figure 11
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 80 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 80 V; V
GS
= 0 V; T
j
= 125 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 15 A; T
j
= 175 °C; see
Figure 12
V
GS
= 10 V; I
D
= 15 A; T
j
= 100 °C; see
Figure 12
V
GS
= 10 V; I
D
= 15 A; T
j
= 25 °C; see
Figure 13
R
G
internal gate resistance f = 1 MHz
(AC)
total gate charge
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
I
D
= 25 A; V
DS
= 40 V; V
GS
= 10 V; see
Figure 14;
see
Figure 15
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
PSMN013-80YS_1
Tested to JEDEC standards where applicable.
Min
73
80
1
-
2
-
-
-
-
-
-
-
-
Typ
-
-
-
-
3
-
-
-
-
-
-
9.7
0.68
Max
-
-
-
4.6
4
3
40
100
100
31
19.8
12.9
-
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
Static characteristics
Dynamic characteristics
Q
G(tot)
-
-
-
-
-
-
I
D
= 25 A; V
DS
= 40 V
V
DS
= 40 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 16
-
-
-
-
V
DS
= 40 V; R
L
= 1.6
Ω;
V
GS
= 10 V;
R
G(ext)
= 4.7
Ω
-
-
-
-
31
37
11
7
4
8
4.8
2420
224
125
20
15
37
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
I
D
= 25 A; V
DS
= 40 V; V
GS
= 10 V; see
Figure 14;
see
Figure 15
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 25 June 2009
5 of 13
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