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74HC191
Presettable synchronous 4-bit binary up/down counter
Rev. 3 — 3 January 2017
Product data sheet
1. General description
The 74HC191 is an asynchronously presettable 4-bit binary up/down counter. It contains
four master/slave flip-flops with internal gating and steering logic to provide asynchronous
preset and synchronous count-up and count-down operation. Asynchronous parallel load
capability permits the counter to be preset to any desired value. Information present on
the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs
when the parallel load (PL) input is LOW. This operation overrides the counting function.
Counting is inhibited by a HIGH level on the count enable (CE) input. When CE is LOW
internal state changes are initiated synchronously by the LOW-to-HIGH transition of the
clock input. The up/down (U/D) input signal determines the direction of counting as
indicated in the function table. The CE input may go LOW when the clock is in either state,
however, the LOW-to-HIGH CE transition must occur only when the clock is HIGH. Also,
the U/D input should be changed only when either CE or CP is HIGH. Overflow/underflow
indications are provided by two types of outputs, the terminal count (TC) and ripple clock
(RC). The TC output is normally LOW and goes HIGH when a circuit reaches zero in the
count-down mode or reaches '15' in the count-up-mode. The TC output will remain HIGH
until a state change occurs, either by counting or presetting, or until U/D is changed. Do
not use the TC output as a clock signal because it is subject to decoding spikes. The TC
signal is used internally to enable the RC output. When TC is HIGH and CE is LOW, the
RC output follows the clock pulse (CP). This feature simplifies the design of multistage
counters as shown in
Figure 5
and
Figure 6.
In
Figure 5,
each RC output is used as the
clock input to the next higher stage. It is only necessary to inhibit the first stage to prevent
counting in all stages, since a HIGH on CE inhibits the RC output pulse. The timing skew
between state changes in the first and last stages is represented by the cumulative delay
of the clock as it ripples through the preceding stages. This can be a disadvantage of this
configuration in some applications.
Figure 6
shows a method of causing state changes to
occur simultaneously in all stages. The RC outputs propagate the carry/borrow signals in
ripple fashion and all clock inputs are driven in parallel. In this configuration the duration of
the clock LOW state must be long enough to allow the negative-going edge of the
carry/borrow signal to ripple through to the last stage before the clock goes HIGH. Since
the RC output of any package goes HIGH shortly after its CP input goes HIGH there is no
such restriction on the HIGH-state duration of the clock. In
Figure 7,
the configuration
shown avoids ripple delays and their associated restrictions. Combining the TC signals
from all the preceding stages forms the CE input for a given stage. An enable must be
included in each carry gate in order to inhibit counting. The TC output of a given stage it
not affected by its own CE signal therefore the simple inhibit scheme of
Figure 5
and
Figure 6
does not apply. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC191: CMOS level
Synchronous reversible counting
Asynchronous parallel load
Count enable control for synchronous expansion
Single up/down control input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC191D
74HC191DB
74HC191PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
SSOP16
Description
plastic small outline package; 16 leads; body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
Version
SOT109-1
SOT338-1
SOT403-1
Type number
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
74HC191
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 3 January 2017
2 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
Fig 3.
Pin configuration SO16
Fig 4.
Pin configuration TSSOP16 and SSOP16
5.2 Pin description
Table 2.
Symbol
D0, D1, D2, D3
Q0, Q1, Q2, Q3
CE
U/D
GND
PL
TC
RC
CP
V
CC
Pin description
Pin
15, 1, 10, 9
3, 2, 6, 7
4
5
8
11
12
13
14
16
Description
data input
flip-flop output
count enable input (active LOW)
up/down input
ground (0 V)
parallel load input (active LOW)
terminal count output
ripple clock output (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
supply voltage
74HC191
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 3 January 2017
3 of 22
NXP Semiconductors
74HC191
Presettable synchronous 4-bit binary up/down counter
6. Functional description
Table 3.
Function table
[1]
Input
PL
parallel load
count up
count down
Hold (do nothing)
[1]
Operating mode
Output
U/D
X
X
L
H
X
CE
X
X
l
l
H
CP
X
X
X
Dn
L
H
X
X
X
Qn
L
H
count up
count down
no change
L
L
H
H
H
H = HIGH voltage level
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
= LOW-to-HIGH clock transition
Table 4.
Input
U/D
H
L
L
L
H
H
[1]
TC and RC Function table
[1]
Terminal count state
CE
H
H
L
H
H
L
X
X
CP
X
X
Q0
H
H
H
L
L
L
Q1
H
H
H
L
L
L
Q2
H
H
H
L
L
L
Q3
H
H
H
L
L
L
L
H
H
H
Output
TC
L
H
RC
H
H
H = HIGH voltage level
L = LOW voltage level
X = don’t care
= one LOW level pulse
= TC goes LOW on a LOW-to-HIGH clock transition
74HC191
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet
Rev. 3 — 3 January 2017
4 of 22
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