HIGH-SPEED 3.3V
64K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
IDT70V08S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
IDT70V08 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
A
15L
A
0L
BUSY
R
64Kx8
MEMORY
ARRAY
70V08
A
15R
A
0R
Address
Decoder
Address
Decoder
A
15L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1.
BUSY
is an input as a Slave (M/S-V
IL
) and an output when it is a Master (M/S-V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
15R
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3740 drw 01
(1)
M/S
NOVEMBER 2017
DSC-3740/10
1
©2017 Integrated Device Technology, Inc.
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V08 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT70V08 is designed to be used as a stand-alone 512K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word system. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 16-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by the chip enables (either
CE
0
or CE
1
)
permit the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using CMOS high-performance technology,
these devices typically operate on only 550mW of power.
The IDT70V08 is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
Pin Configurations
(1,2,3)
Index
NC
NC
A
7L
A
8L
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
A
15L
NC
V
DD
NC
NC
NC
NC
CE
0L
CE
1L
SEM
L
R/W
L
OE
L
Vss
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
72
71
70
69
68
67
66
NC
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
NC
INT
L
BUSY
L
Vss
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
NC
NC
IDT70V08PF
PN100
(4)
100-Pin
TQFP
Top View
(5)
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
NC
A
7R
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
A
15R
NC
Vss
NC
NC
NC
NC
CE
0R
CE
1R
SEM
R
,
R/W
R
OE
R
Vss
Vss
NC
3740 drw 02
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Vss
NC
I/O
7L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
Vss
I/O1
L
I/O
0L
V
DD
Vss
I/O
0R
I/O
1R
I/O
2R
V
DD
I/O
3R
I/O
4R
I/O
5R
I/O
6R
I/O
7R
NC
NC
NC
2
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +4.6
Unit
V
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Commercial
Ambient
Temperature
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
V
DD
3.3V
+
0.3V
3.3V
+
0.3V
3740 tbl 02
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
o
C
C
Industrial
o
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
mA
3740 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
Capacitance
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
(T
A
= +25°C, f = 1.0mhz)
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3740 tbl 03
Output Capacitance
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
15L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
15R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
DD
V
SS
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power (3.3V)
Ground (0V)
3740 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Recommended DC Operating
Conditions
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
____
____
Max.
3.6
0
V
DD
+0.3
(2)
0.8
Unit
V
V
V
V
3740 tbl 05
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.3V.
3
IDT70V08S/L
High-Speed 3.3.V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I – Chip Enable
(1,2)
CE
L
CE
0
V
IL
< 0.2V
V
IH
H
X
>V
CC
-0.2V
X
(3)
CE
1
Mode
Port Selected (TTL Active)
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
3740 tbl 06
V
IH
>V
CC
-0.2V
X
V
IL
X
(3)
<0.2V
NOTES:
1. Chip Enable references are shown above with the actual
CE
0
and CE
1
levels;
CE
is a reference only.
2. 'H' = V
IH
and 'L' = V
IL
.
3. CMOS standby requires 'X' to be either < 0.2V or >V
CC
-0.2V.
Truth Table II – Non-Contention Read/Write Control
Inputs
(1)
CE
(2)
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
Outputs
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
3740 tbl 07
Mode
NOTES:
1. A
0L
— A
15L
≠
A
0R
— A
15R
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
(1)
Inputs
(1)
CE
(2)
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
Outputs
I/O
0-7
DATA
OUT
DATA
IN
______
Mode
Read Semaphore Flag Data Out
Write I/O
0
into Semaphore Flag
Not Allowed
3740 tbl 08
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
7
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
4
IDT70V08S/L
High-Speed 3.3V 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 0.3V)
70V08S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
DD
= 3.6V, V
IN
= 0V to V
DD
CE
(2)
= V
IH
, V
OUT
= 0V to V
DD
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
70V08L
Min.
___
___
___
Max.
10
10
0.4
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
3740 tbl 09
2.4
2.4
NOTES:
1. At V
DD
<
2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6)
(V
DD
= 3.3V ± 0.3V)
Symbol
I
DD
Parameter
Dynamic Operating Current
(Both Ports Active)
Test Condition
CE
= V
IL
, Outputs Disabled
SEM
= V
IH
f = f
MAX
(3)
Version
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
COM'L
IND
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
70V08X15
Com'l Only
Typ.
(2)
Max
170
170
____
____
70V08X20
Com'l & Ind
Typ.
(2)
Max
165
165
____
Unit
mA
260
225
____
____
255
220
____
165
39
39
____
280
60
50
____
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
44
44
____
____
70
60
____
____
mA
39
105
105
____
65
155
140
____
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
DD
- 0.2V
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
DD
- 0.2V
CE
"A"
< 0.2V and
CE
"B"
> V
DD
- 0.2V
(5)
SEM
R
=
SEM
L
> V
DD
- 0.2V
V
IN
> V
DD
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
115
115
____
____
160
145
____
____
mA
105
1.0
0.2
____
155
6
3
____
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
1.0
0.2
____
____
6
3
____
____
mA
0.2
105
105
____
6
150
135
____
I
SB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
115
115
____
____
155
140
____
____
mA
105
150
3740 tbl 10a
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. V
DD
= 3.3V, T
A
= +25°C, and are not production tested. I
DD
DC
= 90mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using “AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
5
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