19-3759; Rev 0; 8/05
KIT
ATION
EVALU
E
BL
AVAILA
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
General Description
The MAX1217 dual, monolithic, 12-bit, 125Msps analog-
to-digital converter (ADC) provides outstanding dynam-
ic performance up to a 250MHz input frequency. The
device operates with conversion rates up to 125Msps
while consuming only 650mW per channel.
At 125Msps and an input frequency of 200MHz, the
MAX1217 achieves an 80dBc spurious-free dynamic
range (SFDR) with excellent 65.3dB signal-to-noise ratio
(SNR) at 200MHz. The SNR remains flat (within 3dB) for
input tones up to 200MHz. This makes the MAX1217
ideal for wideband applications such as communications
receivers, cable head-end receivers, and power-amplifi-
er predistortion in cellular base-station transceivers.
The MAX1217 operates from a single 1.8V power sup-
ply. The analog inputs of each channel are designed
for AC-coupled, differential or single-ended operation.
The ADC also features a selectable on-chip divide-by-2
clock circuit that accepts clock frequencies as high as
250MHz and reduces the phase noise of the input
clock source. A low-voltage differential signal (LVDS)
sampling clock is recommended for best performance.
The converter’s digital outputs are LVDS compatible
and the data format can be selected to be either two’s
complement or offset binary.
The MAX1217 is available in a 100-pin TQFP package
with exposed paddle and is specified over the extend-
ed (-40°C to +85°C) temperature range. Refer to the
MAX1218 (170Msps) and the MAX1219 (210Msps)
data sheets for higher speed, pin-compatible devices.
o
125Msps Conversion Rate
o
Excellent Low-Noise Characteristics
SNR = 67dB at f
IN
= 100MHz
SNR = 65.3dB at f
IN
= 200MHz
o
Excellent Dynamic Range
SFDR = 85dBc at f
IN
= 100MHz
SFDR = 80dBc at f
IN
= 200MHz
o
Single 1.8V Supply
o
1.3W Power Dissipation at f
SAMPLE
= 125Msps
and f
IN
= 10MHz
o
On-Chip Track-and-Hold Amplifier
o
Internal 1.24V Bandgap Reference
o
On-Chip Selectable Divide-by-2 Clock Input
o
LVDS Digital Outputs with Data Clock Output
o
EV Kit Available (Order MAX1217EVKIT)
Features
MAX1217
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
C100E-6
MAX1217ECQ -40°C to +85°C 100 TQFP-EP*
*EP
= Exposed paddle.
Applications
Cable Modem Termination Systems (CMTS)
Cable Digital Return Path Transmitters
Cellular Base-Station Power-Amplifier Linearization
IF and Baseband Digitization
ATE and Instrumentation
Radar Systems
MAX1219
MAX1218
MAX1217
PART
Pin-Compatible Versions
RESOLUTION
(BITS)
12
12
12
SPEED GRADE
(Msps)
210
170
125
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
MAX1217
ABSOLUTE MAXIMUM RATINGS
AV
CC
to AGND ......................................................-0.3V to +2.1V
OV
CC
to OGND .....................................................-0.3V to +2.1V
OV
CC
to AV
CC
.......................................................-0.3V to +0.3V
OGND to AGND ....................................................-0.3V to +0.3V
CLKP, CLKN, INAP, INAN, INBP,
INBN to AGND .....................................-0.3V to (AV
CC
+ 0.3V)
CLKDIV,
T/BA, T/BB
to AGND .................-0.3V to (AV
CC
+ 0.3V)
REFA, REFADJA, REFB, REFADJB
to AGND...............................................-0.3V to (AV
CC
+ 0.3V)
DCOP, DCON, DA0P–DA11P, DA0N–DA11N,
DB0P–DB11P, DB0N–DB11N, ORAP, ORAN,
ORBP, ORBN to OGND .......................-0.3V to (OV
CC
+ 0.3V)
Current into any Pin.............................................................50mA
ESD Voltage on INAP, INAN, INBP, INBN
(Human Body Model).....................................................±750V
ESD Voltage on All Other Pins (Human Body Model)......±2000V
Continuous Power Dissipation (T
A
= +70°C)
100-Pin TQFP (derate 37mW/°C above +70°C).........2963mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 125MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity (Note 2)
Differential Nonlinearity (Note 2)
Transfer Curve Offset
Offset Temperature Drift
ANALOG INPUTS (INAP, INAN, INBP, INBN)
Full-Scale Input Voltage Range
Full-Scale Range Temperature
Drift
Common-Mode Input Range
Differential Input Capacitance
Differential Input Resistance
Full-Power Analog Bandwidth
Reference Output Voltage
Reference Temperature Drift
REFADJ_ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
f
SAMPLE
f
SAMPLE
125
40
MHz
MHz
V
REFADJ_
Used to disable the internal reference
AV
CC
-
0.1
V
CM
C
IN
R
IN
FPBW
V
REF_
T
A
= +25°C, REFADJ_ = AGND
1.18
V
FSR
T
A
= +25°C (Note 2)
1375
1475
150
0.8
3
1.8
800
1.24
65
1.30
1625
mV
P-P
ppm/°C
V
pF
kΩ
MHz
V
ppm/°C
V
N
INL
DNL
V
OS
f
IN
= 10MHz
No missing codes
T
A
= +25°C (Note 2)
12
-2
-1
-3
10
±0.6
±0.3
+2
+1
+3
Bits
LSB
LSB
mV
µV/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE (REFA, REFB, REFADJA, REFADJB)
2
_______________________________________________________________________________________
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
DC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 125MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Clock Pulse-Width Low
Clock Pulse-Width High
Clock Duty Cycle
Aperture Delay
Aperture Jitter
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
Clock Input Common-Mode
Voltage
Clock Differential Input
Resistance
Clock Differential Input
Capacitance
V
CLKCM
R
CLK
C
CLK
T
A
= +25°C (Note 3)
(Note 3)
200
500
1.15
± 0.25
10
±25%
3
mV
P-P
V
kΩ
pF
t
AD
t
AJ
SYMBOL
t
CL
t
CH
CONDITIONS
Figure 5 (Note 3)
Figure 5 (Note 3)
Set by clock-management circuit
Figures 5, 11
Figure 11
MIN
2
2
40 to
60
340
0.15
TYP
MAX
20
20
UNITS
ns
ns
%
ps
ps
RMS
MAX1217
DYNAMIC CHARACTERISTICS (at -1dBFS) (Note 4)
f
IN
= 10MHz
Signal-to-Noise Ratio
SNR
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Effective Number of Bits
ENOB
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Signal-to-Noise Plus Distortion
SINAD
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Spurious-Free Dynamic Range
SFDR
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
f
IN
= 10MHz
Worst Harmonic
(HD2 or HD3)
f
IN
= 65MHz
f
IN
= 100MHz
f
IN
= 200MHz
Two-Tone Intermodulation
Distortion
f
IN1
= 29MHz at -7dBFS
f
IN2
= 31MHz at -7dBFS
f
IN1
= 97MHz at -7dBFS
f
IN2
= 100MHz at -7dBFS
72
72
65
65
10.5
10.5
65.2
65.2
67.7
67.5
67
65.3
11
10.9
10.8
10.6
67.6
67.4
66.8
65.1
88
86
85
80
-88
-86
-85
-80
-92
dBc
-90
-72
-72
dBc
dBc
dB
Bits
dB
TTIMD
_______________________________________________________________________________________
3
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
MAX1217
DC ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= OV
CC
= +1.8V, AGND = OGND = 0, f
SAMPLE
= 125MHz, differential input and differential sine-wave clock signal, 0.1µF
capacitors on REFA and REFB, internal reference, digital output differential R
L
= 100Ω, T
A
= -40°C to +85°C, unless otherwise noted.
Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
Channel Isolation
LVCMOS LOGIC INPUTS (CLKDIV,
T/BA, T/BB)
Input High Voltage
Input Low Voltage
Input Capacitance
LVDS DIGITAL OUTPUTS (DA0P/N–DA11P/N, DB0P/N–DB11P/N, ORAP/N, ORBP/N, DCOP/N)
Differential Output Voltage
Output Offset Voltage
OUTPUT TIMING CHARACTERISTICS
CLK to Data Propagation Delay
CLK to DCO Propagation Delay
DCO to Data Propagation Delay
LVDS Output Rise Time
LVDS Output Fall Time
Output Data Pipeline Delay
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
Output Supply Current
Analog Power Dissipation
Power-Supply Rejection Ratio
AV
CC
OV
CC
I
AVCC
I
OVCC
P
DISS
PSRR
f
IN
= 10MHz
f
IN
= 10MHz
f
IN
= 10MHz
(Note 5)
1.71
1.71
1.8
1.8
600
120
1.3
1
1.89
1.89
725
160
1.6
V
V
mA
mA
W
mV/V
t
PDL
t
CPDL
t
RL
t
FL
t
LATENCY
Figure 5 (Note 3)
Figure 5 (Note 3)
3.7
20% to 80%, C
L
= 5pF
20% to 80%, C
L
= 5pF
Figure 5
1.7
5.2
4.4
350
350
11
5.2
ns
ns
ns
ps
ps
Clock
Cycles
|V
OD
|
V
OS
225
1.125
490
1.310
mV
V
V
IH
V
IL
2
0.8 x
OV
CC
0.2 x
OV
CC
V
V
pF
SYMBOL
CONDITIONS
f
IN
= 200MHz, A
IN
= -1dBFS
MIN
TYP
90
MAX
UNITS
dB
CHANNEL CROSSTALK AND CHANNEL MATCHING SPECIFICATIONS
t
PDL
- t
CPDL
(Note 3)
Note 1:
Values at T
A
= +25°C to +85°C are guaranteed by production test. Values at T
A
< +25°C are guaranteed by design and
characterization.
Note 2:
Static linearity and offset parameters are computed from a best-fit straight line through the code transition points.
The full-scale range (FSR) is defined as 4095 x slope of the line.
Note 3:
Parameter guaranteed by design and characterization; T
A
= -40°C to +85°C.
Note 4:
ENOB and SINAD are computed from a curve fit.
Note 5:
PSRR is measured with the analog and output supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, Dual, 12-Bit, 125Msps ADC for
Broadband Applications
Typical Operating Characteristics
(AV
CC
= OV
CC
= +1.8V, f
SAMPLE
= 125MHz, differential input and differential sine-wave clock, 0.1µF capacitors on REFA and REFB,
digital output differential R
L
= 100Ω, T
A
= +25°C, unless otherwise noted.)
FFT PLOT
(16,384 SAMPLES)
MAX1217 toc01
MAX1217
FFT PLOT
(16,384 SAMPLES)
MAX1217 toc02
FFT PLOT
(16,384 SAMPLES)
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
5
10
6
4 9
7
f
IN
= 100.4867554MHz
f
SAMPLE
= 125MHz
A
IN
= -1.092dBFS
SINAD = 66.84dB
SNR = 66.966dB
THD = -82.247dBc
SFDR = 85.865dBc
HD2 = -87.081dBc
HD3 = -85.865dBc
23
MAX1217 toc03
MAX1217 toc09
MAX1217 toc06
0
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
0
10
10
9
2
8
AMPLITUDE (dB)
f
IN
= 12.4893188MHz
f
SAMPLE
= 125MHz
A
IN
= -0.959dBFS
SINAD = 67.778dB
SNR = 67.9dB
THD = -83.336dBc
SFDR = 86.372dBc
HD2 = -86.372dBc
HD3 = -88.968dBc
3
7
4, 6
5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
IN
= 65.0100708MHz
f
SAMPLE
= 125MHz
A
IN
= -1.001dBFS
SINAD = 67.416dB
SNR = 67.514dB
THD = -83.914dBc
SFDR = 88.662dBc
HD2 = -89.221dBc
HD3 = -88.662dBc
2
4
10
6 8
9 7
5
3
0
20
30
40
FREQUENCY (MHz)
50
60
0
10
20
30
40
FREQUENCY (MHz)
50
60
0
10
20
30
40
FREQUENCY (MHz)
50
60
FFT PLOT
(16,384 SAMPLES)
MAX1217 toc04
FFT PLOT
(16,384 SAMPLES)
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
23
5
4 6 78
9
10
f
IN
= 251.3046265MHz
f
SAMPLE
= 125MHz
A
IN
= -1.066dBFS
SINAD = 64.153dB
SNR = 64.484dB
THD = -75.496dBc
SFDR = 78.786dBc
HD2 = -78.977dBc
HD3 = -78.786dBc
MAX1217 toc05
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 125MHz, A
IN
= -1dBFS)
70
SNR
67
SNR/SINAD (dB)
0
-10
-20
-30
AMPLITUDE (dB)
-40
-50
-60
-70
-80
-90
-100
-110
0
f
IN
= 200.5996704MHz
f
SAMPLE
= 125MHz
A
IN
= -0.992dBFS
SINAD = 65.098dB
SNR = 65.341dB
THD = -77.742dBc
SFDR = 80.122dBc
HD2 = -82.718dBc
HD3 = -80.122dBc
3 2
5 10
8
7
6
4 9
0
64
SINAD
61
58
55
0
10
20
30
40
FREQUENCY (MHz)
50
60
0
50
100
150
200
250
ANALOG INPUT FREQUENCY (MHz)
10
20
30
40
FREQUENCY (MHz)
50
60
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 125MHz, A
IN
= -1dBFS)
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
0
50
100
MAX1217 toc07
SFDR/(-THD) vs. ANALOG INPUT FREQUENCY
(f
SAMPLE
= 125MHz, A
IN
= -1dBFS)
MAX1217 toc08
SNR/SINAD vs. f
SAMPLE
(f
IN
= 65.010071MHz, A
IN
= -1dBFS)
72
70
68
66
SNR/SINAD (dB)
64
62
60
58
56
54
52
50
SINAD
SNR
100
95
90
SFDR/(-THD) (dBc)
85
80
75
70
65
60
55
50
-THD
SFDR
HD2/HD3 (dBc)
HD3
HD2
150
200
250
0
50
100
150
200
250
20
35
50
65
80
95
110
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
f
SAMPLE
(MHz)
_______________________________________________________________________________________
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
