12V High Performance Gate Driver
IR3537
CHL8510
FEATURES
Drives both high‐side and low‐side MOSFETs in a
synchronous buck configuration
Large drivers designed to drive 6nF server class FETs
o
Low‐side driver – 4A source / 6A sink
o
High‐side driver – 3A source / 4A sink
o
Transition times & propagation delays < 20ns
Independent variable gate drive voltage for both
high‐ and low‐side drivers from 4.5V to 13.2V
o
Improves efficiency
o
Compatible with IR controller VGD feature
Integrated bootstrap diode
o
Reduces external component count
Capable of high switching frequencies from 200kHz
up to 1MHz
Configurable PWM modes of operation
o
IR Active Tri‐Level (ATL), disables both MOSFETs
in 30ns with no hold‐off time
o
Generic Tri‐State PWM with hold‐off
Adaptive non‐overlap protection minimizes diode
conduction time
Input supply under voltage protection
Thermally enhanced 10‐pin DFN package
Lead free RoHS compliant package, MSL level 1
DESCRIPTION
The IR3537/CHL8510 is a high efficiency gate driver which
can switch both high‐side and low‐side N‐channel external
MOSFETs in a synchronous buck converter. It is intended
for use with International Rectifier’s Digital PWM
controllers to provide a total voltage regulator (VR)
solution for today’s advanced computing applications.
The IR3537/CHL8510 low‐side driver is capable of rapidly
switching large MOSFETs with low R
DS(on)
and large input
capacitance used in high efficiency designs.
The IR3537/CHL8510 features individual control of
both the high‐and low‐side gate drive voltages from
4.5V to 13.2V. This enables the optimization of switching
and conduction losses in the external MOSFETs. When
used with IR’s proprietary Variable Gate Drive (VGD)
technology, a significant improvement in efficiency is
observed across the entire load range.
The IR3537/CHL8510 can be configured to drive both the
high‐ and low‐side switches from the unique IR fast Active
Tri‐Level (ATL) PWM signal or a generic tri‐state PWM
mode. The IR ATL mode allows the controller to disable
the high‐ and low‐side FETs in less than 30ns without the
need for a dedicated disable pin. This improves VR
transient performance, especially during load release.
The integrated bootstrap diode reduces external
component count. The IR3537/CHL8510 also features
an adaptive non‐overlap control for shoot‐through
protection. This prevents cross conduction of both high‐
side and low‐side MOSFETs and minimizes body diode
conduction time to provide the best in class efficiency.
APPLICATIONS
Multiphase synchronous buck converter for
Server and desktop computers using Intel® and
AMD® VR solutions
High efficiency and compact VRM
High current DC/DC converters
BASIC APPLICATION
PIN DIAGRAM
Figure 1: Basic Applications Circuit
1
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| © 2014 International Rectifier
Figure 2: IR3537/CHL8510 Package Top View
January 9, 2015 | V1.2
12V High Performance Gate Driver
IR3537
CHL8510
FUNCTIONAL BLOCK DIAGRAM
HVCC
BOOT
HI_GATE
MODE
Shoot
Through
Control
SWITCH
LVCC
VCC
PWM
POR,
reference
and
Control
LO_GATE
GND
Figure 3: IR3537/CHL8510 Functional Block Diagram
PIN DESCRIPTIONS
PIN #
1
PIN NAME
BOOT
PIN DESCRIPTION
Floating bootstrap supply pin for the upper gate drive. Connect a bootstrap capacitor between
this pin and the SWITCH pin. The bootstrap capacitor provides the charge to turn on the upper
MOSFET. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing
the capacitor value.
Connect this pin to VCC (+12V) or to a separate supply between 4.5V and 13.2V to provide a lower
gate drive voltage on the high‐side MOSFETs. It is connected to the anode of the internal bootstrap
diode. Place a high‐quality low ESR ceramic capacitor from this pin to GND.
The PWM signal is the control input for the driver from a 1.8V or 3.3V PWM signal. The PWM signal
can enter three distinct states during operation; see the three‐state PWM Input section under
DESCRIPTION for further details. Connect this pin to the PWM output of the controller.
Connect this pin to a +12V bias supply. Place a high quality low ESR ceramic capacitor from this
pin to GND.
Connect this pin to VCC (+12V) or a separate supply voltage between 4.5V and 13.2V to vary the drive
voltage on the low‐side MOSFETs. Place a high‐quality low ESR ceramic capacitor from this pin to GND.
This pin must always be ≤ VCC+0.7Vdc.
Lower gate drive output. Connect to gate of the low‐side power N‐Channel MOSFET.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return
of the driver.
This pin allows selection of the PWM signal voltage for 1.8V or 3.3V normal operation. Floating this pin
configures the driver for IR Active Tri‐Level (ATL) using 1.8V PWM, and connecting this pin to ground
configures the driver for generic active tri‐state operation using 3.3V PWM.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin
provides a return path for the upper gate drive.
Upper gate drive output. Connect to gate of high‐side power N‐Channel MOSFET.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return
of the driver.
2
HVCC
3
PWM
4
VCC
5
6
7
LVCC
LO_GATE
GND
8
MODE
9
10
PAD (11)
SWITCH
HI_GATE
GND
3
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| © 2014 International Rectifier
January 9, 2015 | V1.2
12V High Performance Gate Driver
IR3537
CHL8510
ABSOLUTE MAXIMUM RATINGS
BOOT
PWM
VCC, HVCC
LVCC
LO_GATE
GND
SWITCH
HI_GATE
MODE
ESD – Charged Device Model JESD22‐C101‐C
THERMAL INFORMATION
Thermal Resistance (θ
JC
)
Thermal Resistance (θ
JA
)
1
Maximum Operating Junction Temperature
Maximum Storage Temperature Range
Maximum Lead Temperature (Soldering 10s)
3°C/W
45°C/W
150°C
‐65°C to 150°C
300°C
+35.0V reference to GND,
+15V reference to SWITCH
+7.0V
+15.0V
VCC+0.7Vdc to a maximum of +15.0V
DC: ‐0.3V to <0.3V above Vcc,
<200ns: ‐2V to <0.3V above Vcc
0V+/‐ 0V
DC: ‐0.3V to +15V, <20nS: 25V, <5nS: ‐10V,
<20 ns: ‐4Vdc and <200 ns: ‐2Vdc
DC: SWITCH – 0.3V to 0.3V above VBOOT,
<200ns: SWITCH – 2V to 0.3V above VBOOT
‐0.3V to +15.0V
Passes +/‐1000V
Note 1: θ
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications are not implied.
5
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January 9, 2015 | V1.2
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