19-5309; Rev 0; 6/10
TION KIT
EVALUA BLE
AVAILA
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
General Description
Features
S
Ultra-Low-Power Operation
55mW per Channel at 50Msps
S
Single 1.8V Power Supply
S
Excellent Dynamic Performance
69dBFS SNR at 5.3MHz
140dBc/Hz Near-Carrier SNR at 1kHz Offset
from a 5.3MHz Tone
84dBc SFDR at 5.3MHz
90dB Channel Isolation at 5.3MHz
S
User-Programmable Adjustment and Feature
Selection through an SPI Interface
S
Serial LVDS Outputs with Programmable Current
Drive and Internal Termination
S
Programmable Power Management
S
Internal or External Reference Operation
S
Single-Ended or Differential Clock Input
S
Programmable Output Data Format
S
Built-In Output Data Test Patterns
S
Small, 10mm x 10mm, 144-Lead CTBGA Package
S
Evaluation Kit Available (Order MAX19527EVKIT+)
MAX19527
The MAX19527 is an octal, 12-bit analog-to-digital
converter (ADC), optimized for the low-power and
high-dynamic performance requirements of medical
imaging instrumentation and digital communications
applications. The device operates from a single 1.8V
supply and consumes 440mW (55mW per channel),
while providing a 69dBFS signal-to-noise ratio (SNR) at
a 5.3MHz input frequency. In addition to low operating
power, the device features programmable power man-
agement for idle states and reduced-channel operation.
An internal 1.25V precision bandgap reference sets the
full-scale range of the ADC to 1.5V
P-P
. A flexible refer-
ence structure allows the use of an external reference
for applications requiring greater gain accuracy or a
different input voltage range. A programmable common-
mode voltage reference output is provided to enable
DC-coupled input applications.
Various adjustments and feature selections are avail-
able through programmable registers that are accessed
through the 3-wire serial peripheral interface (SPIK).
A flexible clock input circuit allows for a single-ended,
logic-level clock or a differential clock signal. An on-chip
PLL generates the multiplied (6x) clock required for
the serial LVDS digital outputs. The serial LVDS output
provides programmable test patterns for data timing
alignment and output drivers with programmable current
drive and programmable internal termination.
The device is available in a small, 10mm x 10mm x
1.2mm, 144-lead thin chip ball grid array (CTBGA) pack-
age and is specified for the extended industrial (-40NC to
+85NC) temperature range.
Applications
Ultrasound and Medical Imaging
Instrumentation
Multichannel Communications
ZIF GSM and TD-SCDMA Transceivers
PART
MAX19527EXE+
Ordering Information
TEMP RANGE
-40NC to +85NC
PIN-PACKAGE
144 CTBGA
+Denotes
a lead(Pb)-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
_______________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
ABSOLUTE MAXIMUM RATINGS
AVDD, OVDD to GND ......................................... -0.3V to +2.1V
OGND to GND......................................................-0.3V to +0.3V
IN_+, IN_-, CMOUT, REFIO, REFH,
REFL, CLKIN+, CLKIN- to GND ..............-0.3V to the lower of
(V
AVDD
+ 0.3V) and +2.1V
OUT_+, OUT_-, FRAME+,
FRAME-, CLKOUT+, CLKOUT-,
SHDN,
CS,
SCLK, SDIO to GND .............-0.3V to the lower of
(V
OVDD
+ 0.3V) and +2.1V
Continuous Power Dissipation (T
A
= +70NC)
144-Lead CTBGA (derate 37mW/NC above +70NC)
Multilayer Board ...................................................... 2963mW
Operating Temperature Range ......................... -40NC to +85NC
Junction Temperature ....................................................+150NC
Storage Temperature Range .......................... -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, internal reference, A
IN
= -0.5dBFS, differential clock, V
CLKD
= 1.5V
P-P
, f
CLK
= 50MHz, programmable
registers at default settings (Table 1), T
A
= -40NC to +85NC, typical values are at T
A
= +25NC, unless otherwise noted.) (Note 1)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Input Differential Range
Common-Mode Input Voltage
Range
Input Resistance
INL
DNL
OE
GE
V
DIFF
V
CM
f
IN
= 5.3MHz
f
IN
= 5.3MHz, no missing codes
Internal reference
External reference = 1.25V
IN_+ - IN_-
Q50mV
tolerance
Fixed resistance to GND
R
IN
Differential input resistance, common
mode connected to inputs
Switched capacitance input current,
each input, V
CM
= 1.050V
Fixed capacitance to GND, each input
Fixed differential capacitance
12
Q0.5
Q0.3
Q0.07
Q0.2
1.5
1050
> 100
4
36
1
0.2
1.5
50
25
Figure 5
8.5
MHz
MHz
Clock
Cycles
pF
kI
Q1.7
Q1.0
Q0.7
Q3.0
Bits
LSB
LSB
%FS
%FS
V
P-P
mV
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (IN_+, IN_-) (Figure 2)
Input Current
I
IN
C
INS
FA
Input Capacitance
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Data Latency
C
IND
C
SAMPLE
Switched capacitance, each input
f
CLK
f
CLK
2
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, internal reference, A
IN
= -0.5dBFS, differential clock, V
CLKD
= 1.5V
P-P
, f
CLK
= 50MHz, programmable
registers at default settings (Table 1), T
A
= -40NC to +85NC, typical values are at T
A
= +25NC, unless otherwise noted.) (Note 1)
PARAMETER
DYNAMIC PERFORMANCE
Small-Signal Noise Floor
Near-Carrier Signal-to-Noise
Ratio
SSNF
Analog input < -35dBFS, f
IN
= 5.3MHz
1kHz offset from 5.3MHz full-scale tone,
C
REFIO
= C
REFH/REFL
= 0.1FF
(Figure 3)
8-channel coherent sum
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
Ratio
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion
Full-Power Bandwidth
Overdrive Recovery Time
INTERCHANNEL CHARACTERISTICS
Crosstalk
Gain Matching
Phase Matching
ANALOG OUTPUT (CMOUT)
CMOUT Output Voltage
INTERNAL REFERENCE
REFIO Output Voltage
REFIO Temperature Coefficient
REFH Voltage
REFL Voltage
EXTERNAL REFERENCE
REFIO Input Voltage Range
REFIO Input Resistance
V
REFIN
R
REFIN
+5%/-15% tolerance
1.25
10
Q
20%
V
kI
V
REFIO
TC
REF
V
REFH
V
REFL
Bypass only, no DC load
Bypass only, no DC load
Bypass only, no DC load
1.22
1.25
<
Q60
1.61
0.86
1.28
V
ppm/NC
V
V
V
CMOUT
Default programming state
1.05
1.10
1.15
V
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 5.3MHz
f
IN
= 5.3MHz
-90
Q0.1
Q0.25
dB
dB
Degrees
SNR
SINAD
SFDR
THD
IMD
FPBW
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN
= 5.3MHz at -0.5dBFS
f
IN
= 19.3MHz at -0.5dBFS
f
IN1
= 5.15MHz at -6.5dBFS,
f
IN2
= 5.45MHz at -6.5dBFS
R
SOURCE
= 50I differential
6dB beyond full scale (recover accuracy
to < 1% of full scale)
70.0
66.6
67.0
-69.5
140
147
68.5
68.5
68.2
68.2
84
84
-81
-81
-83
> 500
<1
-72
dB
dB
dBc
dBc
dB
MHz
Clock
Cycles
dBFS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX19527
NCSNR
dBc/Hz
3
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, internal reference, A
IN
= -0.5dBFS, differential clock, V
CLKD
= 1.5V
P-P
, f
CLK
= 50MHz, programmable
registers at default settings (Table 1), T
A
= -40NC to +85NC, typical values are at T
A
= +25NC, unless otherwise noted.) (Note 1)
PARAMETER
Differential Clock Input Voltage
Common-Mode Voltage
SYMBOL
V
CLKD
V
CLKCM
Self-biased
DC-coupled clock signal
Differential, default setting
Input Resistance
R
CLK
Differential, programmable internal
termination selected
Common mode to GND
Input Capacitance
Single-Ended Mode Selection
Threshold (CLKIN-)
Single-Ended Clock Input High
Threshold (CLKIN+)
Single-Ended Clock Input Low
Threshold (CLKIN+)
Input Leakage (CLKIN+)
Input Leakage (CLKIN-)
Input Capacitance (CLKIN+)
DIGITAL INPUTS (SHDN, SCLK, SDIN,
CS)
Input High Threshold
V
IH
Input Low Threshold
Input Leakage
Input Capacitance
DIGITAL OUTPUTS (SDIO)
Output Voltage Low
Output Voltage High
V
OL
V
OH
I
SINK
= 200FA
I
SOURCE
= 200FA
OVDD -
0.2
250
1.125
450
1.375
0.2
V
V
V
IL
I
IH
I
IL
C
DIN
V
IH
= 1.8V
V
IL
= 0V
-5
3
1.5
0.3
+5
C
CLK
Capacitance to GND, each input
CLOCK INPUTS (CLKIN+, CLKIN-)—SINGLE-ENDED MODE (CLKIN- < 0.1V) (Figure 4)
V
IL
V
IH
V
IL
I
IH
I
IL
I
IL
V
IH
= 1.8V
V
IH
= 0V
V
IH
= 0V
-5
-150
3
-50
1.5
0.3
+5
0.1
V
V
V
FA
FA
pF
V
V
FA
pF
CONDITIONS
MIN
TYP
0.4 to 2.0
1.2
1.0 to 1.4
10
0.1
9
3
pF
kI
MAX
UNITS
V
P-P
V
CLOCK INPUTS (CLKIN+, CLKIN-)—DIFFERENTIAL MODE (Figure 4)
LVDS DIGITAL OUTPUTS (OUT_+/OUT_-, CLKOUT+/CLKOUT-, FRAME+/FRAME-)
Differential Output Voltage
Output Offset Voltage
|V
OD
|
V
OS
External R
LOAD
= 100I
External R
LOAD
= 100I
Internal reference, C
REFIO
= 0.1FF,
C
REFH/REFL
= 0.1FF;
Q1%
gain error,
with respect to steady-state gain
Internal reference, C
REFIO
= 0.1FF,
C
REFH/REFL
= 0.1FF;
Q1%
gain error,
with respect to steady-state gain
mV
V
POWER-MANAGEMENT CHARACTERISTICS (Figure 3)
Wake-Up Time from Sleep Mode
t
SWAKE
10
ms
Wake-Up Time from Nap Mode
t
NWAKE
2
Fs
4
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= 1.8V, V
OVDD
= 1.8V, internal reference, A
IN
= -0.5dBFS, differential clock, V
CLKD
= 1.5V
P-P
, f
CLK
= 50MHz, programmable
registers at default settings (Table 1), T
A
= -40NC to +85NC, typical values are at T
A
= +25NC, unless otherwise noted.) (Note 1)
PARAMETER
SCLK Period
SCLK to
CS
Setup Time
SCLK to
CS
Hold Time
SDIO to SCLK Setup Time
SDIO to SCLK Hold Time
SCLK to SDIO Output Data Delay
SYMBOL
t
SCLK
t
CSS
t
CSH
t
SDS
t
SDH
t
SDD
Serial-data write
Serial-data write
Serial-data read
CONDITIONS
MIN
50
10
10
10
0
10
t
SAMPLE
/ t
SAMPLE
/ t
SAMPLE
/
24 - 0.10 24 + 0.05 24 + 0.20
t
SAMPLE
/12
t
SAMPLE
/12
t
SAMPLE
/ t
SAMPLE
/ t
SAMPLE
/
24 - 0.10 24 + 0.05 24 + 0.20
t
SAMPLE
/ t
SAMPLE
/ t
SAMPLE
/
2 + 1.6
2 + 2.3
2 + 3.3
1.7
1.7
8 channels active
Analog Supply Current
I
AVDD
Incremental channel power-down
Nap mode
Sleep mode
8 channels active, external R
LOAD
= 100I
Digital Output Supply Current
I
OVDD
Incremental channel power-down
Nap mode
Sleep mode
8 channels active
Total Power Dissipation
P
TD
Incremental channel power-down
Nap mode
Sleep mode
1.8
1.8
158
-18
13
0.35
87
-7.4
28
< 0.1
440
-46
74
0.8
mW
mA
15
0.5
1.9
1.9
180
mA
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
SERIAL PERIPHERAL INTERFACE (SPI) TIMING (Figure 9, Note 2)
MAX19527
TIMING CHARACTERISTICS (Figures 6 and 7, Note 2)
Data Valid to CLKOUT Rise/Fall
CLKOUT Output-Width High
CLKOUT Output-Width Low
FRAME Rise to CLKOUT Rise
Sample CLK Rise to Frame Rise
POWER REQUIREMENTS
Analog Supply Voltage
Digital Output Supply Voltage
V
AVDD
V
OVDD
V
V
t
OD
t
CH
t
CL
t
DF
t
SF
ns
ns
ns
ns
ns
Note 1:
Specifications are 100% production tested at TA
R
+25NC. Specifications for TA < +25NC are guaranteed by design and
characterization.
Note 2:
Specifications guaranteed by design and characterization.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
