74F175 Quad D-Type Flip-Flop
April 1988
Revised September 2000
74F175
Quad D-Type Flip-Flop
General Description
The 74F175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, LOW.
Features
s
Edge-triggered D-type inputs
s
Buffered positive edge-triggered clock
s
Asynchronous common reset
s
True and complement output
Ordering Code:
Order Number
74F175SC
74F175SJ
74F175PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS009490
www.fairchildsemi.com
74F175
Unit Loading/Fan Out
U.L.
Pin Names
D
0
–D
3
CP
MR
Q
0
–Q
3
Q
0
–Q
3
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs
Complement Outputs
Description
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
−
1 mA/20 mA
Functional Description
The 74F175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master Reset
(MR) will force all Q outputs LOW and Q outputs HIGH
independent of Clock or Data inputs. The 74F175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
Truth Table
Inputs
MR
L
H
H
CP
D
n
X
H
L
Outputs
Q
n
L
H
L
Q
n
H
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F175
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OS
I
CC
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
22.5
4.75
3.75
−0.6
−150
34.0
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
mA
mA
mA
Min
Min
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
0V
CP
=
D
n
=
MR
=
HIGH
3
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74F175
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PHL
t
PLH
Maximum Clock Frequency
Propagation Delay
CP to Q
n
or Q
n
Propagation Delay
MR to Q
n
Propagation Delay
MR to Q
n
100
4.0
4.0
4.5
4.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
140
5.0
6.5
9.0
6.5
6.5
8.5
11.5
8.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
80
3.5
4.0
4.5
4.0
8.5
10.5
15.0
10.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
100
4.0
4.0
4.5
4.0
7.5
9.5
13.0
9.0
Max
MHz
ns
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
CP Pulse Width
HIGH or LOW
MR Pulse Width, LOW
Recovery Time, MR to CP
3.0
3.0
1.0
1.0
4.0
5.0
5.0
5.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
3.0
3.0
1.0
2.0
4.0
5.0
5.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.0
1.0
1.0
4.0
5.0
5.0
5.0
ns
ns
ns
ns
Max
Units
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4
74F175
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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