MB9B500B Series
32-bit Arm
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B500B Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded
control applications.
The MB9B500B Series are based on the Arm
®
Cortex
®
-M3 Processor and on-chip Flash memory and SRAM, and peripheral
functions, including Motor Control Timers, ADCs and Communication Interfaces (USB, CAN, UART, CSIO, I
2
C, LIN).
The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family Peripheral Manual".
Features
32-bit Arm
®
Cortex
®
-M3 Core
Processor version: r2p0
Up to 80 MHz Frequency Operation
Memory Protection Unit (MPU): improve the reliability of an
embedded system
[USB Device]
USB2.0 Full-Speed supported
Max. 6 EndPoint supported
EndPoint
EndPoint
transfer
0 is control transfer
1-5 can be selected bulk-transfer or interrupt-
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
management
EndPoint 1-5 is comprised Double Buffer
[USB Host]
USB2.0 Full/Low speed supported
Bulk-transfer and interrupt-transfer and Isochronous-
transfer support
24-bit System timer (Sys Tick): System timer for OS task
On-chip Memories
[Flash memory]
Up to 512 Kbyte
Read cycle: 0wait-cycle@up to 60 MHz, 2wait-cycle* above
*: Instruction pre-fetch buffer is included. So when CPU
access continuously, it becomes 0wait-cycle
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max.256-byte packet-length supported
Wake-up function supported
CAN Interface (Max. 2 channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Multi-function Serial Interface (Max. 8 channels)
4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels
without FIFO (ch.0-ch.3)
Security function for code protection
[SRAM]
This series contain a total of up to 64 Kbyte on-chip SRAM.
This is composed of two independent SRAM(SRAM0,
SRAM1). SRAM0 is connected to I-code bus and D-code bus
of Cortex-M3 core. SRAM1 is connected to System bus.
SRAM0: Up to 32 Kbyte
SRAM1: Up to 32 Kbyte
USB Interface
USB interface is composed of Device and Host.
PLL for USB is built-in, USB clock can be generated by
multiplication of Main clock.
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
Cypress Semiconductor Corporation
Document Number: 002-05607 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 24, 2017
MB9B500B Series
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control: Automatically control the
transmission by CTS/RTS (only ch.4)
framing errors, and overrun errors)
DMA Controller (8 channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32 bit(4 Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Various error detect functions available (parity errors,
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max. 16 channels)
[12-bit A/D Converter]
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13-16bit length)
LIN break delimiter generate (can be changed 1-4bit length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Successive Approximation Register type
Built-in 3unit
Conversion time: 1.0 μs@5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
Base Timer (Max. 8 channels)
Operation mode is selectable from the followings for each
channel.
conversion: 16steps, for Priority conversion: 4steps)
[I C]
Standard-mode (Max.100 kbps) / Fast-mode (Max.400 kbps)
supported
2
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Multi-function Timer (Max. 2 units)
The Multi-function timer is composed of the following blocks.
External Bus Interface
Supports SRAM, NOR& NAND Flash device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Output compare × 6 ch/unit
A/D activation compare × 3 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
Document Number: 002-05607 Rev. *E
Page 2 of 115
MB9B500B Series
The following function can be used to achieve the motor
control.
General Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover,
the port relocate function is built in. It can set which I/O port
the peripheral function can be allocated.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max. 2 units)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O Ports@120pin
Package
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
The detection edge of the three external event input pins
AIN, BIN and ZIN is configurable.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that
are dynamically selectable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (Two 32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Main Clock :
Sub Clock :
Built-in high-speed CR Clock :
Built-in low-speed CR Clock :
Main PLL Clock
[Resets]
Reset requests from INITX pins
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from sleep mode.
Interval timer: up to 64 s (Max)@ Sub Clock: 32.768 kHz
Watch dog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by the built-in low-
speed CR oscillator. Therefore, ”Hardware" watchdog is active
in any low-power consumption modes except STOP mode.
External Interrupt Controller Unit
Up to 16 external vectors
Include one non-maskable interrupt(NMI)
Clocks generated by CR oscillators are used to supervise
abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Document Number: 002-05607 Rev. *E
Page 3 of 115
MB9B500B Series
Low Voltage Detector (LVD)
This series include 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage has been set, Low
Voltage Detector generates an interrupt or reset.
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three low-power consumption modes supported.
Power Supply
Two Power Supplies
VCC
= 2.7 V to 5.5 V: Correspond to the wide range
voltage.
when USB is used.
SLEEP
TIMER
STOP
USBVCC = 3.0 V to 3.6 V: for USB I/O voltage,
= 2.7 V to 5.5 V: when GPIO is used.*
Document Number: 002-05607 Rev. *E
Page 4 of 115
MB9B500B Series
Contents
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. List of Pin Functions....................................................................................................................................................... 12
5. I/O Circuit Type................................................................................................................................................................ 40
6. Handling Precautions ..................................................................................................................................................... 44
6.1
Precautions for Product Design ................................................................................................................................... 44
6.2
Precautions for Package Mounting .............................................................................................................................. 45
6.3
Precautions for Use Environment ................................................................................................................................ 46
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram ................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 49
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 53
12. Electrical Characteristics ............................................................................................................................................... 58
12.1 Absolute Maximum Ratings ......................................................................................................................................... 58
12.2 Recommended Operating Conditions.......................................................................................................................... 60
12.3 DC Characteristics....................................................................................................................................................... 61
12.3.1 Current rating ............................................................................................................................................................... 61
12.3.2 Pin Characteristics ....................................................................................................................................................... 63
12.4 AC Characteristics ....................................................................................................................................................... 64
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 64
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 65
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 65
12.4.4 Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL) ................................... 66
12.4.5 Operating Conditions of Main PLL (In the case of using built-in high speed CR) ......................................................... 66
12.4.6 Reset Input Characteristics .......................................................................................................................................... 68
12.4.7 Power-on Reset Timing................................................................................................................................................ 68
12.4.8 External Bus Timing ..................................................................................................................................................... 69
12.4.9 Base Timer Input Timing .............................................................................................................................................. 74
12.4.10 CSIO/UART Timing .................................................................................................................................................. 75
12.4.11 External input timing ................................................................................................................................................. 83
12.4.12 Quadrature Position/Revolution Counter timing ........................................................................................................ 84
12.4.13 I
2
C timing .................................................................................................................................................................. 86
12.4.14 ETM timing ............................................................................................................................................................... 87
12.4.15 JTAG timing .............................................................................................................................................................. 88
12.5 12bit A/D Converter ..................................................................................................................................................... 89
12.6 USB characteristics ..................................................................................................................................................... 92
12.7 Low-Voltage Detection Characteristics ........................................................................................................................ 96
12.7.1 Low-Voltage Detection Reset ....................................................................................................................................... 96
12.7.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 96
12.8 Flash Memory Write/Erase Characteristics ................................................................................................................. 97
12.8.1 Write / Erase time......................................................................................................................................................... 97
12.8.2 Erase/write cycles and data hold time .......................................................................................................................... 97
12.9 Return Time from Low-Power Consumption Mode ...................................................................................................... 98
12.9.1 Return Factor: Interrupt ................................................................................................................................................ 98
Page 5 of 115
Document Number: 002-05607 Rev. *E
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