NCP702
200 mA, Ultra-Low Quiescent
Current, Ultra-Low Noise, LDO
Linear Voltage Regulator
Noise sensitive applications such as Phase Locked Loops,
Oscillators, Frequency Synthesizers, Low Noise Amplifiers and other
Precision Instrumentation require very clean power supplies. The
NCP702 is a 200 mA LDO that provides the engineer with a very
stable, accurate voltage with ultra−low noise and very high Power
Supply Rejection Ratio (PSRR), making it suitable for RF
applications. The device doesn’t require an additional noise bypass
capacitor to achieve ultra−low noise performance. In order to optimize
performance for battery operated portable applications, the NCP702
employs an Adaptive Ground Current feature for ultra−low ground
current consumption during light−load conditions.
Features
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5
1
TSOP−5
SN SUFFIX
CASE 483
1
XDFN−6
MX SUFFIX
CASE 711AE
MARKING DIAGRAMS
5
XXXAYW
G
1
X, XXX = Specific Device Code
M = Date Code
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
1
•
Operating Input Voltage Range: 2.0 V to 5.5 V
•
Available in Fixed Voltage Options: 0.8 to 3.5 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Contact Factory for Other Voltage Options
Output Voltage Trimming Step: 2.5 mV
Ultra−Low Quiescent Current of Typ. 10
mA
Ultra−Low Noise: 11
mV
RMS
from 100 Hz to 100 kHz
Very Low Dropout: 140 mV Typical at 200 mA
±2%
Accuracy Over Full Load/Line/Temperature
High PSRR: 68 dB at 1 kHz
Thermal Shutdown and Current Limit Protections
Internal Soft−Start to Limit the Turn−On Inrush Current
Stable with a 1
mF
Ceramic Output Capacitor
Available in TSOP−5 and XDFN 1.5 x 1.5 mm Package
Active Output Discharge for Fast Output Turn−Off
These are Pb−Free Devices
PDAs, Mobile Phones, GPS, Smartphones
Wireless Handsets, Wireless LAN, Bluetooth, Zigbee
Portable Medical Equipment
Other Battery Powered Applications
NCP702
V
IN
C
IN
1
mF
IN
EN
GND
OUT
C
OUT
1
mF
V
OUT
XM
G
PIN CONNECTIONS
IN
GND
EN
5−Pin TSOP−5
(Top View)
1
OUT
N/C
GND
IN
N/C
EN
N/C
1
OUT
Typical Applicaitons
6−Pin XDFN 1.5 x 1.5 mm
(Top View)
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 18 of this data sheet.
Figure 1. Typical Application Schematic
©
Semiconductor Components Industries, LLC, 2013
July, 2013
−
Rev. 3
1
Publication Order Number:
NCP702/D
NCP702
IN
ENABLE
LOGIC
THERMAL
SHUTDOWN
EN
UVLO
BANDGAP
REFERENCE
−
+
INTEGRATED
SOFT−START
MOSFET
DRIVER WITH
CURRENT LIMIT
AUTO LOW
POWER MODE
OUT
EEPROM
EN
ACTIVE
DISCHARGE
GND
Figure 2. Simplified Schematic Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
XDFN 6
1
2
3
4
5
6
1
Pin No.
TSOP−5
5
4
2
3
Pin
Name
OUT
N/C
GND
EN
N/C
IN
Description
Regulated output voltage pin. A small 1
mF
ceramic capacitor is needed from this pin to ground
to assure stability.
Not connected. This pin can be tied to ground to improve thermal dissipation.
Power supply ground.
Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into
shutdown mode.
Not connected. This pin can be tied to ground to improve thermal dissipation.
Input pin. It is recommended to connect a 1
mF
ceramic capacitor close to the device pin.
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Input Voltage (Note 1)
Output Voltage
Enable Input
Output Short Circuit Duration
Maximum Junction Temperature
Storage Temperature
ESD Capability, Human Body Model (Note 2)
ESD Capability, Machine Model (Note 2)
Symbol
V
IN
V
OUT
V
EN
t
SC
T
J(MAX)
T
STG
ESD
HBM
ESD
MM
Value
−0.3
V to 6 V
−0.3
V to V
IN
+ 0.3 V
−0.3
V to V
IN
+ 0.3 V
Indefinite
150
−55
to 150
2000
200
Unit
V
V
V
s
°C
°C
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
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NCP702
Table 3. THERMAL CHARACTERISTICS
(Note 3)
Rating
Thermal Characteristics, TSOP−5,
Thermal Resistance, Junction−to−Air
Thermal Characterization Parameter, Junction−to−Lead (Pin 2)
Thermal Characteristics, XDFN6 1.5 x 1.5 mm
Thermal Resistance, Junction−to−Air
Thermal Characterization Parameter, Junction−to−Board
3. Single component mounted on 1 oz, FR4 PCB with 645 mm
2
Cu area.
Symbol
q
JA
y
JA
q
JA
y
JB
Value
224
115
149
81
Unit
°C/W
°C/W
Table 4. ELECTRICAL CHARACTERISTICS
−40°C
≤
T
J
≤
125°C; V
IN
= V
OUT(NOM)
+ 0.3 V or 2.0 V, whichever is greater; V
EN
= 0.9 V, I
OUT
= 10 mA, C
IN
= C
OUT
= 1
mF.
Typical values are at T
J
= +25°C. Min/Max values are specified for T
J
=
−40°C
and T
J
= 125°C respectively. (Note 4)
Parameter
Operating Input Voltage
Undervoltage lock−out
Output Voltage Accuracy
Line Regulation
V
IN
rising
V
OUT
+ 0.3 V
≤
V
IN
≤
5.5 V, I
OUT
= 0
−
200 mA
V
OUT
+ 0.3 V
≤
V
IN
≤
4.5 V, I
OUT
= 10 mA
V
OUT
+ 0.3 V
≤
V
IN
≤
5.5 V, I
OUT
= 10 mA
Load Regulation
Dropout voltage (Note 5)
Output Current Limit
Quiescent current
Ground current
I
OUT
= 0 mA to 200 mA
I
OUT
= 200 mA, V
OUT(nom)
= 2.5 V
V
OUT
= 90% V
OUT(nom)
I
OUT
= 0 mA
I
OUT
= 2 mA
I
OUT
= 200 mA
Shutdown current (Note 6)
V
EN
≤
0.4 V
V
EN
≤
0.4 V, V
IN
= 4.5 V
EN Pin Threshold Voltage
High Threshold
Low Threshold
EN Pin Input Current
Turn−On Time (Note 7)
Output Voltage Overshoot on
Start−up (Note 8)
Load Transient
Power Supply Rejection Ratio
V
EN
Voltage increasing
V
EN
Voltage decreasing
V
EN
= V
IN
= 5.5 V
C
OUT
= 1.0
mF,
I
OUT
= 1 mA
V
EN
= 0 V to 0.9 V, 0
≤
I
OUT
≤
200 mA
I
OUT
= 1 mA to 200 mA or
I
OUT
= 200 mA to 1 mA in 10
ms,
C
OUT
= 1
mF
V
IN
= 3 V, V
OUT
= 2.5 V
I
OUT
= 150 mA
f = 100 Hz
f = 1 kHz
f = 10 kHz
Test Conditions
Symbol
V
IN
UVLO
V
OUT
Reg
LINE
Reg
LINE
Reg
LOAD
V
DO
I
CL
I
Q
I
GND
I
GND
I
DIS
I
DIS
V
EN_HI
V
EN_LO
I
EN
t
ON
DV
OUT
DV
OUT
PSRR
−30/+30
70
68
53
11
1
160
−
20
−
0.9
0.4
110
300
2
500
nA
ms
%
mV
dB
220
Min
2.0
1.2
−2
290
440
13
140
385
10
60
160
0.005
0.01
1
200
550
16
1.6
Typ
Max
5.5
1.9
+2
Unit
V
V
%
mV/V
mV/V
mV/mA
mV
mA
mA
mA
mA
mA
mA
V
Output Noise Voltage
Active Discharge Resistance
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
V
OUT
= 2.5 V, V
IN
= 3 V, I
OUT
= 200 mA
f = 100 Hz to 100 kHz
V
EN
< 0.4 V
Temperature increasing from T
J
= +25°C
Temperature falling from T
SD
V
N
R
DIS
T
SD
T
SDH
mV
rms
kW
°C
°C
4. Performance guaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T
J
= T
A
= 25_C. Low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
5. Characterized when V
OUT
falls 100 mV below the regulated voltage at V
IN
= V
OUT(NOM)
+ 0.3 V.
6. Shutdown Current is the current flowing into the IN pin when the device is in the disable state.
7. Turn−On time is measured from the assertion of EN pin to the point when the output voltage reaches 0.98 V
OUT(NOM)
8. Guaranteed by design.
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NCP702
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE NOISE (mV/rtHz)
10
V
IN
= 2.0 V
V
OUT
= 0.8 V
C
IN
= C
OUT
= 1
mF
MLCC, X5R,
0402 size
I
OUT
= 1 mA
1
I
OUT
1 mA
10 mA
RMS Output Noise
10 Hz
−
100 kHz
21.74
14.62
10.74
100 Hz
−
100 kHz
21.17
14.07
10.02
0.1
0.01
I
OUT
= 200 mA
I
OUT
= 10 mA
10
100
1k
10k
100k
1M
10M
200 mA
0.001
FREQUENCY (Hz)
Figure 3. Output Voltage Noise Spectral Density for V
OUT
= 0.8 V, C
OUT
= 1
mF
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
1
I
OUT
= 1 mA
0.1
I
OUT
= 200 mA
0.01
V
IN
= 2.0 V
V
OUT
= 0.8 V
C
IN
= C
OUT
= 4.7
mF
MLCC, X7R,
1206 size
I
OUT
= 10 mA
I
OUT
1 mA
10 mA
200 mA
RMS Output Noise
10 Hz
−
100 kHz
14.16
14.20
10.99
100 Hz
−
100 kHz
13.43
13.70
10.48
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 4. Output Voltage Noise Spectral Density for V
OUT
= 0.8 V, C
OUT
= 4.7
mF
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
1
I
OUT
= 1 mA
0.1
I
OUT
= 200 mA
0.01
V
IN
= 2.0 V
V
OUT
= 0.8 V
C
IN
= C
OUT
= 10
mF
MLCC, X7R,
1206 size
I
OUT
= 10 mA
I
OUT
1 mA
10 mA
200 mA
RMS Output Noise
10 Hz
−
100 kHz
12.94
12.78
11.33
100 Hz
−
100 kHz
12.11
12.25
10.83
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 5. Output Voltage Noise Spectral Density for V
OUT
= 0.8 V, C
OUT
= 10
mF
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NCP702
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE NOISE (mV/rtHz)
10
V
IN
= 3.8 V
V
OUT
= 3.3 V
C
IN
= C
OUT
= 1
mF
MLCC, X5R,
0402 size
I
OUT
= 1 mA
I
OUT
= 10 mA
1
I
OUT
1 mA
10 mA
200 mA
RMS Output Noise
10 Hz
−
100 kHz
20.28
16.73
13.70
100 Hz
−
100 kHz
17.87
13.90
10.21
0.1
0.01
I
OUT
= 200 mA
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 6. Output Voltage Noise Spectral Density for V
OUT
= 3.3 V, C
OUT
= 1
mF
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
1
I
OUT
= 1 mA
V
IN
= 3.8 V
V
OUT
= 3.3 V
C
IN
= C
OUT
= 4.7
mF
MLCC, X7R,
1202 size
I
OUT
= 10 mA
I
OUT
1 mA
10 mA
200 mA
RMS Output Noise
10 Hz
−
100 kHz
15.76
17.09
14.51
100 Hz
−
100 kHz
11.82
13.88
11.47
0.1
I
OUT
= 200 mA
0.01
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 7. Output Voltage Noise Spectral Density for V
OUT
= 3.3 V, C
OUT
= 4.7
mF
10
OUTPUT VOLTAGE NOISE (mV/rtHz)
1
I
OUT
= 1 mA
I
OUT
= 200 mA
0.01
V
IN
= 3.8 V
V
OUT
= 3.3 V
C
IN
= C
OUT
= 10
mF
MLCC, X7R,
1206 size
I
OUT
= 10 mA
I
OUT
1 mA
10 mA
200 mA
RMS Output Noise
10 Hz
−
100 kHz
14.87
16.00
14.89
100 Hz
−
100 kHz
10.57
12.65
11.84
0.1
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 8. Output Voltage Noise Spectral Density for V
OUT
= 3.3 V, C
OUT
= 10
mF
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