Low Skew, 1-TO-16 LVCMOS / LVTTL
Fanout Buffer
8343-01
DATA SHEET
General Description
The 8343-01 is a low skew, 1-to-16 LVCMOS/LVTTL Fanout Buffer.
The 8343-01 single ended clock input accepts LVCMOS or LVTTL
input levels. The ICS8343-01 operates at 3.3V, 2.5V and mixed 3.3V
input and 2.5V supply modes over the commercial temperature
range. Guaranteed output and part-to-part skew characteristics
make the 8343-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
Features
• 16 LVCMOS/LVTTL outputs
• One LVCMOS/LVTTL clock input
• CLK can accept the following input levels: LVCMOS, LVTTL
• Maximum output frequency: 200MHz
• Dual output enable inputs facilitates 1-to-16 or 1-to-8 input to
output modes
• All inputs are 5V tolerant
• Output skew: 250ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Full 3.3V and 2.5V or mixed 3.3V core/2.5V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free packaging
• Industrial temperature information available upon request
Block Diagram
VDD1
V
DD1
Pin Assignment
VDD
V
DD
VDD2
V
DD2
CLK
CLK
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q15
Q15
Q14
Q14
Q13
Q13
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
Q8
Q8
OE1
OE1
GND
GND
OE2
OE2
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
(Top View)
8343-01 REVISION B 08/25/14
1
©2014 Integrated Device Technology, Inc.
8343-01 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Name
V
DD1
V
DD1
V
DD1
Q3
Q4
GND
GND
GND
Q5
Q6
Q7
CLK
V
DD
Q8
Q9
Q10
GND
GND
GND
Q11
Q12
V
DD2
V
DD2
V
DD2
Q13
Q14
Q15
OE2
OE1
Q0
Q1
Q2
Power
Power
Power
Output
Output
Power
Power
Power
Output
Output
Output
Input
Power
Output
Output
Output
Power
Power
Power
Output
Output
Power
Power
Power
Output
Output
Output
Input
Input
Output
Output
Output
Pullup
Pullup
Pulldown
Type
Description
Q0 through Q7 output supply pin.
Q0 through Q7 output supply pin.
Q0 through Q7 output supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Power supply ground.
Power supply ground.
Power supply ground.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock input / 5V tolerant.
Core supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Power supply ground.
Power supply ground.
Power supply ground.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Q8 through Q15 output supply pin.
Q8 through Q15 output supply pin.
Q8 through Q15 output supply pin.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
Output enable. When low forces outputs Q8 through Q15 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When low forces outputs Q0 through Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
LVCMOS/LVTTL clock output. 7typical output impedance.
NOTE 1:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin characteristics,
for typical values.
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
2
REVISION B 08/25/14
8343-01 DATA SHEET
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DD1
, V
DD2
= 3.3V
5
V
DD
, V
DD1
, V
DD2
= 3.465V
V
DD1
, V
DD2
= 2.63V
Test Conditions
Minimum
Typical
4
11
9
51
51
7
12
Maximum
Units
pF
pF
pF
k
k
Table 3. Function Table
1
Inputs
OE1
0
1
0
1
OE2
0
0
1
1
Q0:Q7
HiZ
Active
HiZ
Active
Outputs
Q8:Q15
HiZ
HiZ
Active
Active
NOTE 1: OE1 and OE2 are 5V tolerant.
REVISION B 08/25/14
3
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
8343-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
Section , “DC Electrical
Characteristics”
or
AC Electrical Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Storage Temperature, T
STG
Maximum Junction Temperature, TJ
MAX
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDx
+ 0.5V
-65°C to 150°C
125°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ±5%, V
DD1
= V
DD2
= 3.3V ±5% or 2.5V ±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDx
I
DD
I
DDx
Parameter
Core Supply Voltage
Output Supply Voltage
1
Power Supply Current
Output Supply Current
2
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
35
14
Units
V
V
V
mA
mA
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
Table 4B. Power Supply DC Characteristics,
V
DD
= V
DD1
= V
DD2
= 2.5V ±5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDx
I
DD
I
DDx
Parameter
Core Supply Voltage
Output Supply Voltage
1
Power Supply Current
Output Supply Current
2
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
34
13
Units
V
V
mA
mA
NOTE 1: V
DDx
denotes V
DD1
and V
DD2
.
NOTE 2: I
DDx
denotes the sum of I
DD1
and I
DD2
.
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
4
REVISION B 08/25/14
8343-01 DATA SHEET
Table 4C. LVCMOS / LVTTL DC Characteristics,
V
DD
= V
DD1
= V
DD2
= 3.3V ±5% or 2.5V ±5%, V
DD
= 3.3V ±5%,
V
DD1
= V
DD2
= 2.5V±5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High
Voltage
Input Low
Voltage
Input High
Current
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
CLK
OE1, OE2
I
IL
Input Low
Current
CLK
Output High Voltage
1
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
Units
V
V
V
V
A
A
A
A
V
V
0.5
5
5
V
A
A
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
V
IL
I
IH
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD1
= V
DD2
= 3.465V
V
DD1
= V
DD2
= 2.625V
V
DD1
= V
DD2
= 3.465V or
2.625V
-150
-5
2.6
1.8
V
OH
V
OL
I
OZL
I
OZH
Output Low Voltage
Output Tristate Current Low
Output Tristate Current High
NOTE 1: Outputs terminated with 50to V
DDx
/2. See Parameter Measurement Information, “Output Load Test Circuit Diagrams”.
REVISION B 08/25/14
5
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER
FPGA/CPLD
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