Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> 82443ZX

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82443ZX: 产品描述Intel㈢ 440ZX AGPset: Host Bridge/Controller; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小526KB，共116页; 制造商Intel(英特尔); 官网地址http://www.intel.com/

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82443ZX概述

Intel㈢ 440ZX AGPset: Host Bridge/Controller

82443ZX规格参数

参数名称	属性值
厂商名称	Intel(英特尔)
零件包装代码	BGA
包装说明	BGA,
针数	492
Reach Compliance Code	unknown
地址总线宽度	14
边界扫描	NO
总线兼容性	PENTIUM
外部数据总线宽度	64
JESD-30 代码	S-PBGA-B492
长度	35 mm
低功率模式	YES
端子数量	492
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	SQUARE
封装形式	GRID ARRAY
认证状态	Not Qualified
座面最大高度	2.59 mm
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
端子形式	BALL
端子节距	1.27 mm
端子位置	BOTTOM
宽度	35 mm
uPs/uCs/外围集成电路类型	MEMORY CONTROLLER, DRAM
Base Number Matches	1

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Intel

440ZX AGPset:

82443ZX Host Bridge/Controller

Datasheet

November 1998

Order Number: 290650-001

Contents

Architectural Overview ...............................................................................................1-1

Signal Description ......................................................................................................2-1

2.1

2.2

2.3

2.4

2.5

2.6

2.7

3.1

Host Interface Signals...................................................................................2-1

DRAM Interface ............................................................................................2-3

PCI Interface (Primary) .................................................................................2-5

Primary PCI Sideband Interface ...................................................................2-6

AGP Interface Signals...................................................................................2-7

Clocks, Reset, and Miscellaneous ................................................................2-9

Power-Up/Reset Strap Options...................................................................2-10

I/O Mapped Registers ...................................................................................3-2

3.1.1 CONFADD—Configuration Address Register..................................3-2

3.1.2 CONFDATA—Configuration Data Register .....................................3-3

3.1.3 PM2_CTL—ACPI Power Control 2 Control Register .......................3-4

PCI Configuration Space Access..................................................................3-4

3.2.1 Configuration Space Mechanism Overview .....................................3-5

3.2.2 Routing the Configuration Accesses to PCI or AGP ........................3-5

3.2.3 PCI Bus Configuration Mechanism Overview ..................................3-6

3.2.3.1 Type 0 Access ....................................................................3-6

3.2.3.2 Type 1 Access ....................................................................3-6

3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6

3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7

Host-to-PCI Bridge Registers (Device 0) ......................................................3-8

3.3.1 VID—Vendor Identification Register (Device 0).............................3-10

3.3.2 DID—Device Identification Register (Device 0) .............................3-10

3.3.3 PCICMD—PCI Command Register (Device 0) ..............................3-11

3.3.4 PCISTS—PCI Status Register (Device 0) .....................................3-12

3.3.5 RID—Revision Identification Register (Device 0) ..........................3-13

3.3.6 SUBC—Sub-Class Code Register (Device 0) ...............................3-13

3.3.7 BCC—Base Class Code Register (Device 0) ................................3-13

3.3.8 MLT—Master Latency Timer Register (Device 0)..........................3-14

3.3.9 HDR—Header Type Register (Device 0) .......................................3-14

3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14

3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15

3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16

3.3.13 CAPPTR—Capabilities Pointer Register (Device 0) ......................3-16

3.3.14 NBXCFG—NBX Configuration Register (Device 0) .......................3-16

3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19

3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20

3.3.17 PAM[6:0]—Programmable Attribute Map Registers

(Device 0)3-20

3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0) ................3-22

3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24

3.3.20 MBSC—Memory Buffer Strength Control Register

(Device 0).......................................................................................3-25

Register Description...................................................................................................3-1

3.2

3.3

82443ZX Host Bridge

Datasheet

82443ZX

82443ZX概述

82443ZX规格参数

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