74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
December 2013
74VCX00
Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant
Inputs and Outputs
Features
■
1.2V to 3.6V V
CC
supply operation
■
3.6V tolerant inputs and outputs
■
t
PD
■
■
■
■
■
General Description
The VCX00 contains four 2-input NAND gates. This
product is designed for low voltage (1.2V to 3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The VCX00 is fabricated with an advanced CMOS
technology to achieve high-speed operation while main-
taining low CMOS power dissipation.
■
– 2.8ns max. for 3.0V to 3.6V V
CC
Power-off high impedance inputs and outputs
Static Drive (I
OH
/I
OL
)
– ±24mA @ 3.0V V
CC
Uses p
roprietary
noise/EMI reduction circuitry
Latchup performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
>
2000V
– Machine model
>
250V
Leadless DQFN package
Ordering Information
Order Number
74VCX00M
74VCX00BQX
(1)
74VCX00MTC
Package
Number
M14A
MLP14A
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74VCX00 Rev. 1.7.1
www.fairchildsemi.com
74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
Connection Diagrams
Pin Assignments for SOIC and TSSOP
Logic Symbol
IEEE/IEC
Pad Assignments for DQFN
(Top View)
(Bottom View)
Pin Description
Pin Names
A
n
, B
n
O
n
DAP
Description
Inputs
Outputs
No Connect
Note: DAP (Die Attach Pad)
©1999 Fairchild Semiconductor Corporation
74VCX00 Rev. 1.7.1
www.fairchildsemi.com
2
74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage
HIGH or LOW State
(2)
V
CC
= 0V
I
IK
I
OK
Parameter
Rating
–0.5V to +4.6V
–0.5V to 4.6V
–0.5V to V
CC
+ 0.5V
–0.5V to 4.6V
–50mA
–50mA
+50mA
±50mA
±100mA
–65°C to +150°C
DC Input Diode Current, V
I
<
0V
DC Output Diode Current
V
O
<
0V
V
O
>
V
CC
I
OH
/ I
OL
DC Output Source/Sink Current
I
CC
or GND DC V
CC
or Gound Current per Supply Pin
T
STG
Storage Temperature Range
Note:
2. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
(3)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
V
O
I
OH
/ I
OL
Power Supply Operating
Input Voltage
Parameter
Rating
1.2V to 3.6V
–0.3V to 3.6V
0V to V
CC
±24mA
±18mA
±6mA
±2mA
± 100µA
–40°C to +85°C
10ns/V
Output Voltage, HIGH or LOW State
Output Current
V
CC
=
3.0V to 3.6V
V
CC
=
2.3V to 2.7V
V
CC
=
1.65V to 2.3V
V
CC
=
1.4V to 1.6V
V
CC
=
1.2V
T
A
∆
t /
∆
V
Free Air Operating Temperature
Minimum Input Edge Rate, V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
Note:
3. Floating or unused inputs must be held HIGH or LOW
©1999 Fairchild Semiconductor Corporation
74VCX00 Rev. 1.7.1
www.fairchildsemi.com
3
74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
V
CC
(V)
2.7–3.6
2.3–2.7
1.65–2.3
1.4–1.6
1.2
Conditions
Min
2.0
1.6
0.65
×
V
CC
0.65
×
V
CC
0.65
×
V
CC
Max
Units
V
V
IL
LOW Level Input Voltage
2.7–3.6
2.3–2.7
1.65–2.3
1.4–1.6
1.2
0.8
0.7
0.35
×
V
CC
0.35
×
V
CC
0.05 x V
CC
I
OH
=
–100µA
I
OH
=
–12mA
I
OH
=
–18mA
I
OH
=
–24mA
I
OH
=
–100µA
I
OH
=
–6mA
I
OH
=
–12mA
I
OH
=
–18mA
I
OH
=
–100µA
I
OH
=
–6mA
I
OH
=
–100µA
I
OH
=
–2mA
I
OH
=
–100µA
I
OL
=
100µA
I
OL
=
12mA
I
OL
=
18mA
I
OL
=
24mA
I
OL
=
100µA
I
OL
=
12mA
I
OL
=
18mA
I
OL
=
100µA
I
OL
=
6mA
I
OL
=
100µA
I
OL
=
2mA
I
OL
=
100µA
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V,
V
I
=
V
IH
or V
IL
0
≤
(V
I
, V
O
)
≤
3.6V
V
I
=
V
CC
or GND
V
CC
≤
(V
I
, V
O
)
≤
3.6V
(4)
V
IH
=
V
CC
–0.6V
V
CC
– 0.2
2.2
2.4
2.2
V
CC
– 0.2
2.0
1.8
1.7
V
CC
– 0.2
1.25
V
CC
– 0.2
1.05
V
CC
– 0.2
0.2
0.4
0.4
0.55
0.2
0.4
0.6
0.2
0.3
0.2
0.35
0.05
±5.0
±10
10
20
±20
750
V
V
OH
HIGH Level Output Voltage
2.7–3.6
2.7
3.0
3.0
2.3–2.7
2.3
2.3
2.3
1.65–2.3
1.65
1.4–1.6
1.4
1.2
V
V
OL
LOW Level Output Voltage
2.7–3.6
2.7
3.0
3.0
2.3–2.7
2.3
2.3
1.65–2.3
1.65
1.4–1.6
1.4
1.2
V
I
I
I
OZ
I
OFF
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Power-OFF Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
1.4–3.6
1.4–3.6
0
1.4–3.6
2.7–3.6
µA
µA
µA
µA
µA
Note:
4. Outputs disabled or 3-STATE only.
©1999 Fairchild Semiconductor Corporation
74VCX00 Rev. 1.7.1
www.fairchildsemi.com
4
74VCX00 — Low Voltage Quad 2-Input NAND Gate with 3.6V Tolerant Inputs and Outputs
AC Electrical Characteristics
(5)
T
A
=
–40°C to
+85°C
Symbol
t
PHL
, t
PLH
Parameter
Propagation Delay
V
CC
(V)
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
1.2
Conditions
C
L
=
30pF, R
L
=
500Ω
Min.
0.6
0.8
1.0
Max.
2.8
3.7
7.4
14.8
37.0
0.5
0.5
0.75
Units
ns
Figure
Number
Fig. 1
Fig. 2
C
L
=
15pF, R
L
=
2kΩ
C
L
=
30pF, R
L
=
500Ω
1.0
1.5
Fig. 3
Fig. 4
ns
t
OSHL
, t
OSLH
Output to Output
Skew
(6)
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
1.2
C
L
=
15pF, R
L
=
2kΩ
1.5
1.5
Note:
5. For C
L
=
50pF, add approximately 300ps to the AC Maximum specification.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
T
A
=
25°C
Symbol
V
OLP
Parameter
Quiet Output Dynamic Peak V
OL
V
CC
(V)
1.8
2.5
3.3
Conditions
C
L
=
30pF, V
IH
=
V
CC
,
V
IL
=
0V
C
L
=
30pF, V
IH
=
V
CC
,
V
IL
=
0V
C
L
=
30pF, V
IH
=
V
CC
,
V
IL
=
0V
Typical
0.25
0.6
0.8
–0.25
–0.6
–0.8
1.5
1.9
2.2
Unit
V
V
OLV
Quiet Output Dynamic Valley V
OL
1.8
2.5
3.3
V
V
OHV
Quiet Output Dynamic Valley V
OH
1.8
2.5
3.3
V
Capacitance
T
A
=
+25°C
Symbol
C
IN
C
OUT
C
PD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
Conditions
V
I
=
0V or V
CC
, V
CC
=
1.8V, 2.5V or 3.3V
V
I
=
0V or V
CC
, V
CC
=
1.8V, 2.5V or 3.3V
V
I
=
0V or V
CC
, f
=
10 MHz, V
CC
=
1.8V, 2.5V
or 3.3V
Typical
6
7
20
Units
pF
pF
pF
©1999 Fairchild Semiconductor Corporation
74VCX00 Rev. 1.7.1
www.fairchildsemi.com
5
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