CY7C1440AV33
36-Mbit (1M × 36) Pipelined Sync SRAM
36-Mbit (1M × 36) Pipelined Sync SRAM
Features
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Functional Description
The CY7C1440AV33 SRAM integrates 1M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
X
and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The CY7C1440AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click
here.
Supports bus operation up to 250 MHz
Available speed grades are 250 and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V/3.3 V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1440AV33 available in Pb-free 100-pin TQFP package,
Pb-free 165-ball FBGA package.
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.6
475
120
167 MHz
3.4
375
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05383 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 2, 2016
CY7C1440AV33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 8
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Address Table ................................. 8
Linear Burst Address Table ......................................... 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Truth Table for Read/Write ............................................ 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 11
Disabling the JTAG Feature ...................................... 11
Test Access Port (TAP) ............................................. 11
PERFORMING A TAP RESET .................................. 11
TAP REGISTERS ...................................................... 11
TAP Instruction Set ................................................... 11
TAP Controller State Diagram ....................................... 13
TAP Controller Block Diagram ...................................... 14
TAP Timing ...................................................................... 14
TAP AC Switching Characteristics ............................... 15
3.3 V TAP AC Test Conditions ....................................... 15
3.3 V TAP AC Output Load Equivalent ......................... 15
2.5 V TAP AC Test Conditions ....................................... 15
2.5 V TAP AC Output Load Equivalent ......................... 15
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Maximum Ratings ........................................................... 19
Operating Range ............................................................. 19
Electrical Characteristics ............................................... 19
Capacitance .................................................................... 20
Thermal Resistance ........................................................ 20
AC Test Loads and Waveforms ..................................... 20
Switching Characteristics .............................................. 21
Switching Waveforms .................................................... 22
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagrams .......................................................... 27
Acronyms ........................................................................ 29
Document Conventions ................................................. 29
Units of Measure ....................................................... 29
Document History Page ................................................. 30
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Document Number: 38-05383 Rev. *N
Page 3 of 33
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