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LCMXO3L-1300E-5UWG36ITR50: 产品描述FPGA - Field Programmable Gate Array MachXO3, 1280 LUTs 1.2V; 产品类别可编程逻辑器件可编程逻辑; 文件大小2MB，共85页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

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LCMXO3L-1300E-5UWG36ITR50概述

FPGA - Field Programmable Gate Array MachXO3, 1280 LUTs 1.2V

LCMXO3L-1300E-5UWG36ITR50规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	Lattice(莱迪斯)
包装说明	VFBGA,
Reach Compliance Code	compliant
ECCN代码	EAR99
JESD-30 代码	R-PBGA-B36
长度	2.541 mm
可配置逻辑块数量	160
端子数量	36
组织	160 CLBS
封装主体材料	PLASTIC/EPOXY
封装代码	VFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
可编程逻辑类型	FIELD PROGRAMMABLE GATE ARRAY
座面最大高度	0.576 mm
最大供电电压	1.26 V
最小供电电压	1.14 V
标称供电电压	1.2 V
表面贴装	YES
端子形式	BALL
端子节距	0.4 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	2.487 mm
Base Number Matches	1

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MachXO3™ Family

Data Sheet

FPGA-DS-02032-2.0

January 2018

MachXO3™ Family

Data Sheet

Contents

Acronyms in This Document .................................................................................................................................................................. 6

1. Introduction..................................................................................................................................................................................... 7

1.1.

Features ................................................................................................................................................................................. 8

1.1.1. Solutions............................................................................................................................................................................ 8

1.1.2. Flexible Architecture ....................................................................................................................................................... 8

1.1.3. Advanced Packaging........................................................................................................................................................ 8

1.1.4. Pre-Engineer ed Source Synchronous I/O .................................................................................................................... 8

1.1.5. High Performance, Flexible I/O Buffer......................................................................................................................... 8

1.1.6. Flexible On-Chip Clocking............................................................................................................................................... 8

1.1.7. Non-volatile, Multi-time Programmable ..................................................................................................................... 8

1.1.8. TransFR Reconfiguration................................................................................................................................................ 8

1.1.9. Enhanced System Level Support................................................................................................................................... 8

1.1.10.

Applications ................................................................................................................................................................. 8

1.1.11.

Low Cost Migration Path........................................................................................................................................... 8

2. Architecture ...................................................................................................................................................................................10

2.1.

Architecture Overview ......................................................................................................................................................10

2.2.

PFU Blocks ...........................................................................................................................................................................12

2.2.1. Slices ................................................................................................................................................................................12

2.2.2. Modes of Operation......................................................................................................................................................14

2.2.3. RAM Mode ......................................................................................................................................................................14

2.2.4. ROM Mode......................................................................................................................................................................14

2.3.

Routing .................................................................................................................................................................................15

2.4.

Clock/Control Distribution Network ................................................................................................................................15

2.4.1. sysCLOCK Phase Locked Loops (PLLs) ........................................................................................................................17

2.5.

sysMEM Embedded Block RAM Memory ......................................................................................................................20

2.5.1. sysMEM Memory Block................................................................................................................................................20

2.5.2. Bus Size Matching..........................................................................................................................................................20

2.5.3. RAM Initialization and ROM Operation.....................................................................................................................20

2.5.4. Memory Cascading........................................................................................................................................................20

2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes .....................................................................................................21

2.5.6. FIFO Configuration ........................................................................................................................................................22

2.5.7. Memory Core Reset ......................................................................................................................................................22

2.5.8. EBR Asynchronous Reset..............................................................................................................................................23

2.6.

Programmable I/O Cells (PIC)...........................................................................................................................................24

2.7.

PIO.........................................................................................................................................................................................26

2.7.1. Input Register Block ......................................................................................................................................................26

2.7.2. Output Register Block...................................................................................................................................................26

2.7.3. Tri-state Register Block.................................................................................................................................................27

2.8.

Input Gearbox .....................................................................................................................................................................27

2.9.

Output Gearbox..................................................................................................................................................................29

2.10. sysIO Buffer .........................................................................................................................................................................31

2.10.1.

Typical I/O Behavior during Power-up..................................................................................................................31

2.10.2.

Supported Standards ...............................................................................................................................................31

2.10.3.

sysIO Buffer Banks ....................................................................................................................................................33

2.11. Hot Socketing ......................................................................................................................................................................34

2.12. On-chip Oscillator...............................................................................................................................................................34

2.13. Embedded Hardened IP Functions..................................................................................................................................34

2.13.1.

Hardened I

C IP Core................................................................................................................................................35

2.13.2.

Hardened SPI IP Core ...............................................................................................................................................36

2.13.3.

Hardened Timer/Counter........................................................................................................................................38

2.14. User Flash Memory (UFM) ...............................................................................................................................................39

2.15. Standby Mode and Power Saving Options ....................................................................................................................39

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.0

MachXO3™ Family

Data Sheet

2.16. Power On Reset ..................................................................................................................................................................40

2.17. Configuration and Testing ................................................................................................................................................41

2.17.1.

IEEE 1149.1-Compliant Boundary Scan Testability.............................................................................................41

2.17.2.

Device Configuration................................................................................................................................................41

2.18. TraceID .................................................................................................................................................................................43

2.19. Density Shifting...................................................................................................................................................................43

3. DC and Switching Characteristics...............................................................................................................................................44

3.1.

Absolute Maximum Rating ...............................................................................................................................................44

3.2.

Recommended Operating Conditions ............................................................................................................................44

3.3.

Power Supply Ramp Rates ................................................................................................................................................44

3.4.

Power-On-Reset Voltage Levels ......................................................................................................................................45

3.5.

Hot Socketing Specifications ............................................................................................................................................45

3.6.

Programming/Erase Specifications .................................................................................................................................45

3.7.

ESD Performance................................................................................................................................................................46

3.8.

DC Electrical Characteristics .............................................................................................................................................46

3.9.

Static Supply Current – C/E Devices................................................................................................................................47

3.10. Programming and Erase Supply Current – C/E Devices ...............................................................................................48

3.11. sysIO Recommended Operating Conditions ...................................................................................................................49

3.12. sysIO Single-Ended DC Electrical Characteristics ...........................................................................................................50

3.13. sysIO Differential Electrical Characteristics ...................................................................................................................51

3.13.1.

LVDS ............................................................................................................................................................................51

3.13.2.

LVDS Emulation.........................................................................................................................................................51

3.13.3.

BLVDS..........................................................................................................................................................................52

3.13.4.

LVPECL.........................................................................................................................................................................53

3.13.5.

MIPI D-PHY Emulation..............................................................................................................................................54

3.14. Typical Building Block Function Performance – C/E Devices

....................................................................................57

3.14.1.

Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ............................................................................................57

3.14.2.

Register-to-Register Performance .........................................................................................................................57

3.15. Derating Logic Timing........................................................................................................................................................57

3.16. Maximum sysIO Buffer Performance .............................................................................................................................58

3.17. MachXO3L/LF External Switching Characteristics – C/E Devices...............................................................................59

3.18. sysCLOCK PLL Timing .........................................................................................................................................................64

3.19. NVCM/Flash Download Time ...........................................................................................................................................66

3.20. JTAG Port Timing Specifications ......................................................................................................................................66

3.21. sysCONFIG Port Timing Specifications............................................................................................................................68

3.22. I

C Port Timing Specifications ..........................................................................................................................................69

3.23. SPI Port Timing Specifications ..........................................................................................................................................69

3.24. Switching Test Conditions.................................................................................................................................................69

4. Signal Descriptions........................................................................................................................................................................70

4.1.

Pin Information Summary.................................................................................................................................................72

5. MachXO3 Part Number Description..........................................................................................................................................77

6. Ordering Information...................................................................................................................................................................78

6.1.

MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging.......78

References...............................................................................................................................................................................................82

Revision History......................................................................................................................................................................................83

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.0

MachXO3™ Family

Data Sheet

Figures

Figure 2.1. Top View of the MachXO3L/LF-1300 Device.................................................................................................................10

Figure 2.2. Top View of the MachXO3L/LF-4300 Device.................................................................................................................11

Figure 2.3. PFU Block Diagram.............................................................................................................................................................12

Figure 2.4. Slice Diagram ......................................................................................................................................................................13

Figure 2.5. Primary Clocks for MachXO3L/F Devices.......................................................................................................................16

Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices ..............................................................................................17

Figure 2.7. PLL Diagram ........................................................................................................................................................................18

Figure 2.8. sysMEM Memory Primitives ............................................................................................................................................21

Figure 2.9. Memory Core Reset...........................................................................................................................................................23

Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram......................................................................................23

Figure 2.11. Group of Four Programmable I/O Cells .......................................................................................................................25

Figure 2.12. Sentry Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..............................................27

Figure 2.13. Input Gearbox ..................................................................................................................................................................28

Figure 2.14. Output Gearbox ...............................................................................................................................................................30

Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900 and

MachXO3L/LF-9400 Banks IO Banks...................................................................................................................................................33

Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks ...................................................................................................33

Figure 2.17. Embedded Func tion Block Interface ............................................................................................................................35

Figure 2.18. I

C Core Block Diagram ...................................................................................................................................................35

Figure 2.19. SPI Core Block Diagram...................................................................................................................................................37

Figure 2.20. Timer/Counter Block Diagram.......................................................................................................................................38

Figure 3.1. LVDS Using External Resistors (LVDS25E)......................................................................................................................51

Figure 3.2. BLVDS Multi-point-Output Example ...............................................................................................................................52

Figure 3.3. Differential LVPECL ............................................................................................................................................................53

Figure 3.4. MIPI D-PHY Input Using External Resistors ...................................................................................................................54

Figure 3.5. MIPI D-PHY Output Using External Resistors ................................................................................................................55

Figure 3.6.Receiver GDDR71_RX. Wavefor ms ..................................................................................................................................64

Figure 3.7. Transmitter GDDR71_TX. Waveforms............................................................................................................................64

Figure 3.8. JTAG Port Timing Waveforms ..........................................................................................................................................67

Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards .......................................................................................................69

Tables

Table 1.1. MachXO3L/LF Family Selection Guide............................................................................................................................... 9

Table 2.1. Resources and Modes Available per Slice.......................................................................................................................12

Table 2.2. Slice Signal Descriptions.....................................................................................................................................................13

Table 2.3. Number of Slices Required For Implementing Distributed RAM................................................................................14

Table 2.4. PLL Signal Descriptions .......................................................................................................................................................19

Table 2.5. sysMEM Block Configurations...........................................................................................................................................20

Table 2.6. EBR Signal Descriptions ......................................................................................................................................................21

Table 2.7. Programmable FIFO Flag Ranges ......................................................................................................................................22

Table 2.8. PIO Signal List.......................................................................................................................................................................26

Table 2.9. Input Gearbox Signal List ...................................................................................................................................................27

Table 2.10. Output Gearbox Signal List..............................................................................................................................................29

Table 2.11. Supported Input Standards..............................................................................................................................................32

Table 2.12. Supported Output Standards ..........................................................................................................................................32

Table 2.13. Available MCLK Fr equencies ...........................................................................................................................................34

Table 2.14. I

C Core Signal Description..............................................................................................................................................36

Table 2.15. SPI Core Signal Description..............................................................................................................................................37

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.0

MachXO3™ Family

Data Sheet

Table 2.16. Timer/Counter Signal Description..................................................................................................................................39

Table 2.17. MachXO3L/LF Power Saving Features Description.....................................................................................................40

Table 3.1. Absolute Maximum Rating

1,2,3

..........................................................................................................................................44

Table 3.2. Recommended Operating Conditions

............................................................................................................................44

Table 3.3. Power Supply Ramp Rates

...............................................................................................................................................44

Table 3.4. Power-On Reset Voltage Levels

1,2,3,4,5

..............................................................................................................................45

Table 3.5. Hot Socketing Specifications

1,2,3

.......................................................................................................................................45

Table 3.6. Programming/Erase Specifications ..................................................................................................................................45

Table 3.7. Static Supply Current – C/E Devices

1,2,3,6

.........................................................................................................................47

Table 3.8. Programming and Erase Supply Current – C/E Devices

1,2,3,4

........................................................................................48

Table 3.9. sysIO Recommended Operating Conditions...................................................................................................................49

Table 3.10. sysIO Single-Ended DC Electrical Charateristics

1,2

.......................................................................................................50

Table 3.11. LVDS25E DC Conditions ...................................................................................................................................................52

Table 3.12. BLVDS DC Condition

........................................................................................................................................................53

Table 3.13. LVPECL DC Conditions ......................................................................................................................................................54

Table 3.14. MIPI DC Conditions

..........................................................................................................................................................55

Table 3.15. MIPI D-PHY Output DC Conditions

...............................................................................................................................56

Table 3.16. MachXO3L/LF External Switching Characteristics – C/E Devices

1,2,3,4,5,6,10

.............................................................59

Table 3.17. NVCM/Flash Download Time

1,2,3

....................................................................................................................................66

Table 3.18. sysCONFIG Port Timing Specifications ..........................................................................................................................68

Table 3.19. I

C Port Timing Specification

1,2

.......................................................................................................................................69

Table 3.20. SPI Port Timing Specifications.........................................................................................................................................69

Table 3.21. Test Fixture Required Components, Non-Terminated Interfaces ............................................................................69

Table 4.1. Signal Descriptions ..............................................................................................................................................................70

Table 4.2. MachXO3L/LF-9400C ..........................................................................................................................................................76

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.0

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