4:4 Differential-to-LVPECL/LVDS
Clock Multiplexer
ICS859S0424I
DATA SHEET
General Description
The ICS859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock
Multiplexer which can operate up to 3GHz. The outputs for this
device can either be programmed to give LVPECL or LVDS levels.
The ICS859S0424I has four selectable differential PCLKx, nPCLKx
clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL,
LVDS or CML levels. The fully differential architecture and low
propagation delay make it ideal for use in clock distribution circuits.
Features
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High speed 4:1 differential multiplexer with a 1:4 fanout buffer
Four programmable differential LVPECL or LVDS output pairs
Four selectable differential PCLKx, nPCLKx input pairs
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
Maximum output frequency: 3GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx inputs
Part-to-part skew: 100ps (maximum)
Propagation delay: 555ps (typical) @ 3.3V
Additive phase jitter, RMS: 0.22ps (typical) @ 3.3V
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
OEA
Pullup
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
Pin Assignment
CLK_SEL0
CLK_SEL1
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
OEA
OEB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
V
EE
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
V
CC_TAP
SEL_OUT
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
PCLK2
Pulldown
nPCLK2
Pullup/Pulldown
PCLK3
Pulldown
nPCLK3
Pullup/Pulldown
QA0
0
0
nQA0
QA1
0
1
nQA1
QB0
1
0
nQB0
QB1
1
1
nQB1
ICS859S0424I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
OEB
Pullup
SEL_OUT
Pullup
ICS859S0424BGI REVISION A OCTOBER 12, 2011
1
©2011 Integrated Device Technology, Inc.
ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 2. Pin Descriptions
Number
1,
2
3
4
5
6
7
8
9
10
11
12
13
14
15, 16
17, 18
19, 20
21, 22
23
24
Name
CLK_SEL0,
CLK_SEL1
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
OEA
OEB
SEL_OUT
V
CC_TAP
nQB1, QB1
nQB0, QB0
nQA1, QA1
nQA0, QA0
V
EE
V
CC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Power
Power
Type
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup
Pullup
Pullup
Description
Clock select inputs. See Table 4A. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Output enable pin for Bank A outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
Output enable pin for Bank B outputs. See Table 4B.
LVCMOS/LVTTL interface levels.
Output select pin. When LOW, selects LVDS levels. When HIGH, selects
LVPECL levels. LVCMOS/LVTTL interface levels. See Table 1B.
Power supply pin. See Table 1A.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Differential output pair. LVPECL or LVDS interface levels.
Negative supply pin.
Power supply pin.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 3. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
VCC/2
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Input Pullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
50
Maximum
Units
pF
k
Ω
k
Ω
k
Ω
ICS859S0424BGI REVISION A OCTOBER 12, 2011
2
©2011 Integrated Device Technology, Inc.
ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Function Tables
Table 4A. Clock Input Function Table
Inputs
CLK_SEL1
0
0
1
1
CLK_SEL0
0
1
0
1
Outputs
Qx[0:1], nQx[0:1]
PCLK0, nPCLK0 (default)
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
Table 4B. V
CC_TAP
Function Table
Outputs
Qx[0:1], nQx[0:1]
LVPECL
LVPECL
LVDS
LVDS
Output Level Supply
2.5V
3.3V
2.5V
3.3V
V
CC_TAP
V
CC
V
CC
V
CC
Float
Table 4C. SEL_OUT Function Table
Input
SEL_OUT
1
0
Outputs
Qx[0:1], nQx[0:1]
LVPECL (default)
LVDS
Table 4D. Output Enable Function Table
Inputs
OEA, OEB
0
1
Outputs
Qx[0:1], nQx[0:1]
Low/High
Normal Operation (default)
ICS859S0424BGI REVISION A OCTOBER 12, 2011
3
©2011 Integrated Device Technology, Inc.
ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
10mA
15mA
82.8°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
CC_TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
72
5
Units
V
V
mA
mA
Table 5B. LVPECL Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
EE
I
CC_TAP
Parameter
Power Supply Voltage
Power Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
66
5
Units
V
V
mA
mA
Table 5C. LVDS Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
I
CC_TAP
Parameter
Positive Supply Voltage
Power Supply Current
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
140
5
Units
V
mA
mA
Table 5D. LVDS Power Supply DC Characteristics,
V
CC
= V
CC_TAP
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
V
CC_TAP
I
CC
I
CC_TAP
Parameter
Positive Supply Voltage
Positive Supply Voltage
Power Supply Current
Power Supply Current
4
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
Maximum
2.625
2.625
130
5
Units
V
V
mA
mA
ICS859S0424BGI REVISION A OCTOBER 12, 2011
©2011 Integrated Device Technology, Inc.
ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
Table 5E. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.465V
V
CC
= 2.625V
Input Low Voltage
CLK_SEL0,
CLK_SEL1
I
IH
Input High Current
OEA, OEB,
SEL_OUT
CLK_SEL0,
CLK_SEL1
I
IL
Input Low Current
OEA, OEB,
SEL_OUT
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-150
µA
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
10
µA
µA
V
CC
= 3.465V
V
CC
= 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
V
IL
Table 5F. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.4
V
CC
– 2.0
0.6
1.3
V
CC
V
CC
– 0.9
V
CC
– 1.7
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: Outputs terminated with 50
Ω
to V
CC
– 2V.
Table 5G. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High Current
PCLK0, nPCLK0,
PCLK1, nPCLK1
PCLK0, PCLK1
Input Low Current
nPCLK0, nPCLK1
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.4
V
CC
– 2.0
0.4
1.3
V
CC
V
CC
– 0.9
V
CC
– 1.5
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: Outputs terminated with 50
Ω
to V
CC
– 2V.
ICS859S0424BGI REVISION A OCTOBER 12, 2011
5
©2011 Integrated Device Technology, Inc.
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