74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 4 — 24 June 2013
Product data sheet
1. General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behaviour. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Input levels:
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C.
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HC193D
74HC193DB
74HC193N
74HC193PW
74HCT193D
74HCT193DB
74HCT193N
74HCT193PW
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO16
SSOP16
DIP16
TSSOP16
SO16
SSOP16
DIP16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil)
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic dual in-line package; 16 leads (300 mil)
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT338-1
SOT38-4
SOT403-1
SOT109-1
SOT338-1
SOT38-4
SOT403-1
Type number
4. Functional diagram
15
D0
1
D1
10
D2
9
D3
TCU
COUNTER
TCD
12
13
CPU
14
MR
FLIP-FLOPS
Q0
3
2
Q1
6
Q2
7
Q3
001aag405
11
5
4
PL
CPU
CPD
PL
11
5
4
14
MR
D0
15
D1
1
D2
10
D3
9
12
13
TCU
TCD
CPD
3
Q0
2
Q1
6
Q2
7
Q3
001aag409
Fig 1. Functional diagram
Fig 2. Logic symbol
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
2 of 30
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Product data sheet
Rev. 4 — 24 June 2013
4 of 30
74HC_HCT193
NXP Semiconductors
D0
D1
D2
D3
PL
CPU
TCU
All information provided in this document is subject to legal disclaimers.
SD
T
Q
T
SD
Q
T
SD
Q
T
SD
Q
Presettable synchronous 4-bit binary up/down counter
FF1
Q
RD
FF2
Q
RD
FF3
Q
RD
FF4
Q
RD
74HC193; 74HCT193
TCD
CPD
MR
Q0
Q1
Q2
Q3
001aag412
© NXP B.V. 2013. All rights reserved.
Fig 4. Logic diagram
NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
74HC193
74HCT193
D1
1
2
3
4
5
6
7
8
001aaf408
74HC193
74HCT193
D1
Q1
Q0
CPD
CPU
Q2
Q3
GND
1
2
3
4
5
6
7
8
001aag406
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
D1
Q1
Q0
CPD
CPU
Q2
Q3
GND
1
2
3
4
5
6
7
8
001aag407
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
74HC193
74HCT193
16 V
CC
15 D0
14 MR
13 TCD
12 TCU
11 PL
10 D2
9
D3
Q1
Q0
CPD
CPU
Q2
Q3
GND
Fig 5. Pin configuration SO16
Fig 6. Pin configuration TSSOP16
and SSOP16
Fig 7. Pin configuration DIP16
5.2 Pin description
Table 2.
Symbol
D0
D1
D2
D3
Q0
Q1
Q2
Q3
CPD
CPU
GND
PL
TCU
TCD
MR
V
CC
[1]
Pin description
Pin
15
1
10
9
3
2
6
7
4
5
8
11
12
13
14
16
Description
data input 0
data input 1
data input 2
data input 3
flip-flop output 0
flip-flop output 1
flip-flop output 2
flip-flop output 3
count down clock input
[1]
count up clock input
[1]
ground (0 V)
asynchronous parallel load input (active LOW)
terminal count up (carry) output (active LOW)
terminal count down (borrow) output (active LOW)
asynchronous master reset input (active HIGH)
supply voltage
LOW-to-HIGH, edge triggered.
74HC_HCT193
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 4 — 24 June 2013
5 of 30
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