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7142LA100L48B

产品描述SRAM 16K(2KX8)CMOS DUALPORT RA
产品类别存储   
文件大小219KB,共17页
制造商IDT(艾迪悌)
官网地址http://www.idt.com/
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7142LA100L48B概述

SRAM 16K(2KX8)CMOS DUALPORT RA

7142LA100L48B规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
IDT(艾迪悌)
产品种类
Product Category
SRAM
Shipping RestrictionsThis product may require additional documentation to export from the United States.
RoHSN
封装 / 箱体
Package / Case
LCC-48
系列
Packaging
Tube
高度
Height
1.78 mm
长度
Length
14.2 mm
宽度
Width
14.22 mm
工厂包装数量
Factory Pack Quantity
34

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HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
On-chip port arbitration logic (IDT7132 only)
BUSY
output flag on IDT7132;
BUSY
input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
OL-
I/O
7L
I/O
Control
I/O
Control
I/O
OR-
I/O
7R
m
BUSY
L
(1,2)
A
10L
A
0L
Address
Decoder
11
BUSY
R
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
LOGIC
CE
R
OE
R
R/W
R
2692 drw 01
NOTES:
1. IDT7132 (MASTER):
BUSY
is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor of 270Ω.
NOVEMBER 2015
1
©2015 Integrated Device Technology, Inc.
DSC-2692/21

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