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74AUP1G373GW125

产品描述Latches 1.8V LOW-POW D
产品类别半导体    逻辑   
文件大小824KB,共25页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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74AUP1G373GW125概述

Latches 1.8V LOW-POW D

74AUP1G373GW125规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
NXP(恩智浦)
产品种类
Product Category
Latches
RoHSDetails
Number of Circuits1 Circuit
Logic TypeCMOS
Logic FamilyAUP
PolarityNon-Inverting
Quiescent Current500 nA
Number of Output Lines1 Line
High Level Output Current- 4 mA
传播延迟时间
Propagation Delay Time
22.1 ns, 12.3 ns
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
800 mV
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 125 C
封装 / 箱体
Package / Case
SOT-363
系列
Packaging
Cut Tape
系列
Packaging
MouseReel
系列
Packaging
Reel
FunctionTransparent
高度
Height
1 mm
长度
Length
2.2 mm
输出类型
Output Type
3-State
类型
Type
D-Type
宽度
Width
1.35 mm
安装风格
Mounting Style
SMD/SMT
Number of Channels1 Channel
Number of Input Lines1 Line
工作电源电压
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Reset TypeNo Reset
工厂包装数量
Factory Pack Quantity
3000
单位重量
Unit Weight
0.000212 oz

文档预览

下载PDF文档
74AUP1G373
Low-power D-type transparent latch; 3-state
Rev. 6 — 4 July 2012
Product data sheet
1. General description
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While
the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is
LOW, the latch stores the information that was present at the D-input one set-up time
preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of
the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the
high-impedance OFF-state. Operation of input pin OE does not affect the state of the
latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C

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