74VHC574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 180 MHz (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4
µA
(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
OLP
= 0.9V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
DESCRIPTION
The 74VHC574 is an advanced high-speed
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to the logic states that were
setup at the D inputs.
While the (OE) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
Figure 1: Pin Connection And IEC Logic Symbols
O
et
l
so
b
ro
P
e
uc
d
s)
t(
while high level the outputs will be in a high
impedance state.
The Output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
O
-
so
b
te
le
ro
P
T&R
uc
d
s)
t(
74VHC574MTR
74VHC574TTR
November 2004
Rev. 4
1/14
74VHC574
Table 4: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 20
±
20
±
25
±
75
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time (note 1) (V
CC
= 3.3
±
0.3V)
(V
CC
= 5.0
±
0.5V)
Parameter
1) V
IN
from 30% to 70% of V
CC
O
et
l
so
b
ro
P
e
uc
d
s)
t(
O
-
s
b
te
le
o
Value
2 to 5.5
0 to 5.5
ro
P
uc
d
s)
t(
Unit
V
V
V
°C
ns/V
0 to V
CC
0 to 100
0 to 20
-55 to 125
3/14
74VHC574
Table 7: AC Electrical Characteristics
(Input t
r
= t
f
= 3ns)
Test Condition
Symbol
Parameter
V
CC
(V)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PZL
t
PZH
Output Enable
Time
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
t
PLZ
t
PHZ
t
w
t
s
t
h
f
MAX
Output Disable
Time
Clock Pulse Width
HIGH or LOW
Setup Time D to CK
HIGH or LOW
Hold Time D to CK
HIGH or LOW
Maximum Clock
Frequency
3.3
(*)
3.3
(*)
3.3
(*)
5.0
(**)
3.3
(*)
Value
T
A
= 25°C
Min.
Typ.
8.5
11.0
5.6
7.1
8.2
10.7
5.9
7.4
11.0
7.1
Max.
13.2
16.7
8.6
10.6
12.8
16.3
9.0
11.0
15.0
10.1
5.0
5.0
-40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
15.5
19.0
10.0
12.0
15.0
18.5
10.5
12.5
17.0
-55 to 125°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
15.5
19.0
10.0
12.0
15.0
18.5
ns
Unit
C
L
(pF)
15
50
15
50
15
50
15
50
50
50
t
PLH
t
PHL
Propagation Delay
Time
CH to Q
5.0
(**)
3.3
(*)
5.0
(**)
3.3
(*)
3.3
(*)
5.0
(**)
5.0
(**)
15
50
15
50
t
OSLH
t
OSHL
Output to Output
Skew time (note 1)
(*) Voltage range is 3.3V
±
0.3V
(**) Voltage range is 5.0V
±
0.5V
Note 1: Parameter guaranteed by design. t
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Table 8: Capacitive Characteristics
O
Symbol
C
IN
C
OUT
C
PD
et
l
so
b
ro
P
e
3.3
(*)
5.0
(**)
50
50
uc
d
)-
(s
t
b
O
125
75
180
115
so
3.5
3.5
1.5
1.5
t
le
65
45
110
75
P
e
11.5
5.0
5.0
3.5
3.5
1.5
1.5
ro
1.0
1.0
uc
d
10.5
12.5
17.0
11.5
5.0
5.0
3.5
3.5
1.5
1.5
s)
t(
ns
ns
ns
ns
ns
80
50
65
45
110
75
1.5
1.0
1.5
1.0
ns
MHz
130
85
1.5
1.0
Test Condition
T
A
= 25°C
Min.
Typ.
7
9
28
Max.
10
Value
-40 to 85°C
Min.
Max.
10
-55 to 125°C
Min.
Max.
10
pF
pF
pF
Unit
Parameter
Input Capacitance
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/8 (per
Flip-Flop)
5/14
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
