74ABT574A
Octal D-type flip-flop; 3-state
Rev. 2 — 23 November 2012
Product data sheet
1. General description
The 74ABT574A high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT574A is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The clock input (CP) and output enable input (OE) control gates, control the two
sections of the device independently. The state of each data input (Dn, one set-up time
before the Low-to-High clock transition) is transferred to the Q output of the corresponding
flip-flop.
When OE is Low, the stored data appears at the outputs. When OE is High, the outputs
are in the High-impedance “off” state, which means they do not drive or load the bus.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the clock operation.
2. Features and benefits
74ABT574A is flow-through pinout version of 74ABT374A
Inputs and outputs on opposite side of package allow easy
interface to microprocessors
3-State outputs for bus interfacing
Power-on 3-state
Power-on reset
Common output enable
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Live insertion/extraction permitted.
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT574AN
74ABT574AD
74ABT574ADB
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
DIP20
SO20
SSOP20
TSSOP20
Description
plastic dual in-line package; 20 leads (300 mil)
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT146-1
SOT163-1
SOT339-1
SOT360-1
Type number
74ABT574APW
40 C
to +85
C
4. Functional diagram
11
1
11
2
3
4
5
6
7
8
9
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna798
C1
EN
2
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
8
9
3
4
5
6
7
1D
19
18
17
16
15
14
13
12
mna446
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
CP
FF2
FF3
FF4
FF5
FF6
FF7
FF8
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
001aah077
Fig 3.
74ABT574A
Logic diagram
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 23 November 2012
2 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
$%7$
2(
9
&&
4
4
4
4
4
4
4
4
&3
DDD
'
'
'
'
'
'
'
'
*1'
$%7$
2(
'
'
'
'
'
'
'
'
*1'
DDD
9
&&
4
4
4
4
4
4
4
4
&3
Fig 4.
Pin configuration DIP20 and SO20
Fig 5.
Pin configuration SSOP20 and TSSOP20
5.2 Pin description
Table 2.
Symbol
OE
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock pulse input (active rising edge)
3-state flip-flop output
supply voltage
74ABT574A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 23 November 2012
3 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
OE
Load and read register
Load register and disable output
L
L
H
H
[1]
H = HIGH voltage level;
h = HIGH voltage level one setup time before the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one setup time before the HIGH-to-LOW CP transition;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
Operating mode
CP
Dn
l
h
l
h
Internal
flip-flop
L
H
L
H
Output
Qn
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
128
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
Conditions
Min
4.5
0
2.0
-
32
Typ
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
Unit
V
V
V
V
mA
74ABT574A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 23 November 2012
4 of 16
NXP Semiconductors
74ABT574A
Octal D-type flip-flop; 3-state
Table 5.
Operating conditions
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol
I
OL
t/V
T
amb
Parameter
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
-
0
40
Typ
-
-
-
Max
64
5
+85
Unit
mA
ns/V
C
9. Static characteristics
Table 6.
Symbol
V
IK
V
OH
Static characteristics
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OH
=
3
mA
V
CC
= 5.0 V; I
OH
=
3
mA
V
CC
= 4.5 V; I
OH
=
32
mA
V
OL
V
OL(pu)
I
I
I
OFF
I
O(pu/pd)
I
OZ
LOW-level output
voltage
power-up LOW-level
output voltage
input leakage current
power-off leakage
current
V
CC
= 4.5 V; I
OL
= 64 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; I
O
= 1 mA;
V
I
= GND or V
CC
V
CC
= 5.5 V; V
I
= V
CC
or GND
V
CC
= 0 V; V
I
or V
O
4.5 V
[2]
[1]
25
C
Typ
0.9
2.9
3.4
2.4
0.42
0.13
Max
-
-
-
-
0.55
0.55
1.2
2.5
3.0
2.0
-
-
-
-
-
40 C
to +85
C
Unit
Min
1.2
2.5
3.0
2.0
-
-
-
-
-
Max
-
-
-
-
0.55
0.55
1.0
100
50
V
V
V
V
V
V
A
A
A
0.01 1.0
5.0
5.0
100
50
power-up/power-down V
CC
= 2.0 V; V
O
= 0.5 V;
output current
V
I
= GND or V
CC
; OE HIGH
OFF-state output
current
V
CC
= 5.5 V; V
I
= V
IL
or V
IH
V
O
= 2.7 V
V
O
= 0.5 V
-
50
-
[3]
5.0
5.0
5.0
50
-
50
40
-
50
-
180
-
-
-
-
50
-
50
40
250
30
250
1.5
A
A
A
mA
A
mA
A
mA
I
LO
I
O
I
CC
output leakage current HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
output current
supply current
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
outputs HIGH-state
outputs LOW-state
outputs disabled
180
-
-
-
100
24
100
0.5
250
30
250
1.5
I
CC
additional supply
current
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
[4]
-
74ABT574A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 23 November 2012
5 of 16
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