NCN49597
Power Line Communication
Modem
The NCN49597 is a powerful spread frequency shift keying
(S−FSK) communication system−on−chip (SoC) designed for
communication in hostile environments.
It combines a low power ARM Cortex M0 processor with a high
precision analogue front end. Based on 4800 baud S−FSK
dual−channel technology, it offers an ideal compromise between speed
and robustness.
Pin−compatible with its predecessor, the AMIS−49587, this new
generation chip extends the communication frequency range to cover
all CENELEC bands for use in applications such as e−metering, home
automation and street lighting. The NCN49597 benefits for more than
10 years of field experience in e−metering and delivers innovative
features such as a smart synchronization and in−band statistics.
Fully reprogrammable, the modem firmware can be updated in the
field. Multiple royalty−free firmware options are available from
ON Semiconductor; refer to the separate datasheets for details. The
configurable GPIOs allow connecting peripherals such as LCDs or
metering ICs.
Features
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1
52
QFN52 8x8, 0.5P
CASE 485M
MARKING DIAGRAM
52
1
XXXXYZZ
NCN 49597
C597−901
•
Power Line Communication (PLC) Modem for 50 Hz, 60 Hz and DC
•
•
•
•
•
Mains
Embedded ARM Cortex M0 Processor
10 General Purpose IOs Controllable by Software
Embedded 32 kB RAM
Embedded 2 kB ROM Containing Boot Loader
Hardware Compliant with CENELEC EN 50065−1 and EN 50065−7
Half Duplex S−FSK Channel, Data Rate Selectable:
300 – 600 – 1200 – 2400 – 4800 baud (@ 50 Hz);
360 – 720 – 1440 – 2880 – 5760 baud (@ 60 Hz)
Programmable Carrier Frequencies in CENELEC A, B, C and D
Band
UART for Interfacing with an Application Microcontroller
Power Supply 3.3 V
Wide Junction Temperature Range: −40°C to +125°C
XXXX
Y
ZZ
= Date Code
= Plant Identifier
= Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 29 of this data sheet.
•
•
•
•
Available Firmware Options
•
ON−PL110 − Mesh Networking with Collision
Avoidance and Error Correction
•
Complete Handling of Protocol Layers (physical,
MAC, LLC)
Typical Applications
•
•
•
•
•
AMR: Remote Automated Meter Reading
Building Automation
Solar Power Control and Monitoring
Street Light Control and Monitoring
Transmission of Alerts (fire, gas leak, water leak)
©
Semiconductor Components Industries, LLC, 2017
1
January, 2017 − Rev. 4
Publication Order Number:
NCN49597/D
NCN49597
APPLICATION
Application Example
C
8
R
8
R
7
3V3_D
R
6
C
6
3V3_A
3V3_D
C
16
VDDA
C
17
VDD
12 V
C
9
12 V
C
7
−B
12
Vuc OutA
5
19
U
1
R
12
TXD
D
1
MAINS
6
VCC
7
U
2
4
−A
R
10
D
2
C
10
R
5
R
4
C
4
3V3_D
C
3
TX_OUT
RXD
BR 0
BR 1
RESB
OutB 8
9
10
11 1
Enable
NCS5651
VEE
3
+A
13
2 20 14
15
+B Vcom
Rlim
GNDuC Vwarn
Application
&
Metering
Micro
Controller
R
9
C
5
C
11
Tr
1:2
R
14
TX_ENB
NCN49597
RX_OUT
RX_IN
VDD1V8
R
2
D
3
D
4
R
11
3V3_A
R
3
C
2
C
1
R
1
REF_OUT
SEN
C
15
C
DREF
D
5
C
12
ZC_IN
EXT_CLK_E
XTAL_IN
XTAL_OUT
VSSA
Y
1
C
13
C
14
Figure 1. Typical Application for the NCN49597 S−FSK Modem
Figure 1 shows an S−FSK PLC modem built around the
NCN49597. The design is a good starting point for a
CENELEC. EN 50065−1−compliant system; for further
information refer to the referenced design manual.
This design is not galvanically isolated; safety must be
considered when interfacing to a microcontroller or a PC.
For synchronization the mains is coupled in via a 1 MW
resistor; the Schottky diode pair D
5
clamps the voltage
within the input range of the zero crossing detector.
In the receive path a 2
nd
order high pass filter blocks the
mains frequency. The corner point − defined by C
1
, C
2
, R
1
and R
2
− is designed at 10 kHz. In the transmit path a 3
th
order low pass filter built around the NCS5651 power
operational amplifier suppresses the 2
nd
and 3
rd
harmonics
to be in line with the CENELEC EN50065−1 specification.
The filter components are tuned for a space and mark
frequency of 63.3 and 74 kHz respectively. The output of the
amplifier is coupled through DC blocking capacitor C
10
to
a 2:1 transformer Tr. The high voltage capacitor C
11
couples
the secondary of this transformer to the mains.
High−energetic transients from the mains are clamped by
the protection diode combination D
3
, D
4
, together with D
1
,
D
2
.
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VSS
NCN49597
Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION
Component
C
1
, C
2
C
5
, C
DREF
C
7
, C
9
, C
16
, C
17
C
3
C
4
C
6
C
8
C
10
C
11
C
12
C
13
, C
14
C
15
R
1
R
2
R
3
R
9
R
4
R
5
R
6
R
7
R
8
R
10
R
11
R
12
, R
13
D
1
, D
2
D
3
, D
4
D
5
Y1
Tr
U1
U2
Function and Remarks
High pass receive filter
V
COM
& V
REF_OUT
ceramic decoupling
Supply decoupling
TX_OUT signal coupling
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Transmission signal coupling cap;
1 A
RMS
ripple @ 70 kHz
High voltage coupling; 630 VDC
Zero crossing noise suppression
Crystal load capacitor
Internal 1.8 V supply decoupling; ceramic
High pass receive filter
High pass receive filter
High pass receive filter
Line driver current limitation setting
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Low pass transmit filter
Line transients protection; 0.5 W
Zero crossing coupling
Pull up
High−current Schottky clamp diodes
Unidirectional TVS
Dual low−current Schottky clamp diode
Crystal
2:1 signal transformer
PLC modem
Power operational amplifier
NCN49597
NCS5651
Value
1.5
1
100
470
470
68
3
10
220
100
22
1
22
11
10
10
3.3
10
8.2
500
3
0.47
1
10
MBRA340
P6SMB6.8AT3G
BAS70−04
48 MHz
50 ppm
Tolerance
±10%
−20 +80%
−20 +80%
±20%
±10%
±10%
±10%
±20%
±20%
±20%
±20%
−20 +80%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±1%
±10%
±10%
±10%
Unit
nF
mF
nF
nF
pF
pF
pF
mF
nF
pF
pF
mF
kW
kW
kW
kW
kW
kW
kW
W
kW
W
MW
kW
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NCN49597
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
POWER SUPPLY PINS VDD, VDDA, VSS, VSSA
Absolute max. digital power supply
Absolute max. analog power supply
Absolute max. difference between digital and analog power supply
Absolute max. difference between digital and analog ground
CLOCK PINS XIN, XOUT
Absolute maximum input for the clock input pin (Note 1)
Absolute maximum voltage at the clock output pin (Note 1)
V
XIN_ABSM18
V
XOUT_ABSM18
V
SS
− 0.2
V
SS
− 0.2
V
DD18
+ 0.2
V
DD18
+ 0.2
V
V
V
DD_ABSM
V
DDA_ABSM
V
DD
− V
DDA_ABSM
V
SS
− V
SSA_ABSM
V
SS
− 0.3
V
SSA
− 0.3
−0.1
−0.1
3.9
3.9
0.1
0.1
V
V
V
V
Symbol
Min
Max
Unit
NON 5 V SAFE PINS: TX_OUT, ALC_IN, RX_IN, RX_OUT, REF_OUT, ZC_IN, TDO, SCK, SDO, SCB
Absolute maximum input for normal digital inputs and analog inputs
Absolute maximum voltage at any output pin
Maximum peak input current at the zerocrossing input pin
Maximum average input current at the zerocrossing input pin (1 ms)
V
N5VSIN_ABSM
V
N5VSOUT_ABSM
Imp
ZC_IN
Imavg
ZC_IN
V
SS
− 0.3
V
SS
− 0.3
−20
−2
V
DD
+ 0.3
V
DD
+ 0.3
20
2
V
V
mA
mA
5 V SAFE PINS: TX_ENB, TXD, RXD, BR0, BR1, IO0..IO9, RESB, TDI, TCK, TMS, TRSTB, TEST, SDI
Absolute maximum input for digital 5 V safe pins configured as input (Note 2)
Absolute maximum voltage at 5 V safe pin configured as output (Note 2)
V
5VSIN_ABSM
V
5VSOUT_ABSM
V
SS
− 0.3
V
SS
− 0.3
5.5
V
DD
+ 0.3
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The upper maximum voltage rating on the clock pins XIN and XOUT is specified with respect to the output voltage of the internal core voltage
regulator. The tolerance of this voltage regulator must be taken into account. In case an external clock is used, care must be taken not to
damage the XIN pin.
2. The direction (input or output) of configurable pins (IO0…IO9) depends on the firmware.
Normal Operating Conditions
Operating ranges define the limits for functional
operation and parametric characteristics of the device as
described in the Electrical Characteristics section and for the
reliability specifications.
Table 3. OPERATING RANGES
Rating
Power supply voltage range (VDDA and VDD pins)
Junction Temperature Range
Ambient Temperature Range
Total cumulative dwell time outside the normal power
supply voltage range or the ambient temperature under bias,
must be less than 0.1 percent of the useful life.
Symbol
V
DD
, V
DDA
T
J
T
A
Min
3.0
−40
−40
Max
3.6
125
115
Unit
V
°C
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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NCN49597
PIN DESCRIPTION − QFN Package
NC
NC
TX_OUT
ALC_IN
NC
NC
VDDA
VSSA
RX_OUT
RX_IN
NC
REF_OUT
NC
52
51
50
49
48
47
46
45
44
43
42
41
40
ZC_IN
NC
IO3
IO4
IO5
IO0
TDO
TDI
TCK
TMS
TRST
IO6
IO8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
21
22
23
24
25
26
16
39
38
37
36
35
NCN49597
34
33
32
31
30
29
28
27
NC
NC
TX_EN
TEST
RES
NC
IO1
BR0
BR1
SEN
IO2
CSB
SDO
Figure 2. QFN Pin−out of NCN49597 (top view)
Table 4. NCN49597 QFN PIN FUNCTION DESCRIPTION
Pin Number
1
3..5, 12..14
6, 33
13, 23
7
8
9
10
11
15
16
17
18
19
20
21
Pin Name
ZC_IN
IO3..IO7
IO0, IO1
IO8, IO9
TDO
TDI
TCK
TMS
TRSTB
EXT_CLK_E
DATA/PRES
XIN
XOUT
VDD1V8
VSS
VDD
I/O
In
In/Out
In/Out
In/Out
Out
In
In
In
In
In
Out
In
Out
Type
A
D, 5VS, ST
D, 5VS, ST
D, 5VS, ST, PD
D
D, 5VS, PD, ST
D, 5VS, PD
D, 5VS, PD
D, 5VS, PD, ST
D, 5VS, PD, ST
D, 5VS, OD
A, 1.8 V
A, 1.8 V
P
P
P
Description
50/60 Hz input for mains zero crossing detection
General purpose I/O’s (Note 3)
General purpose I/O’s (Notes 3 and 4)
General purpose IO (Notes 3 and 9)
JTAG test data output
JTAG test data input (Note 7)
JTAG test clock (Note 7)
JTAG test mode select (Note 7)
JTAG test reset (active low) (Note 8)
External clock enable input
Output of transmitted data (DATA) or PRE_SLOT signal (PRES)
Crystal oscillator input
Crystal oscillator output (output must be left floating when XIN is
driven by an external clock)
1.8 V regulator output. A decoupling capacitor of at least 1
mF
is
required for stability
Digital ground
3.3 V digital supply
3. The direction and function of the general−purpose I/O’s is controlled by the firmware. Depending on the firmware behavior, a general−pur-
pose IO (GPIO) used as an output may appear as an open−drain, push−pull or open−source pin. Refer to the firmware documentation
for details.
4. During boot (i.e., before firmware has been uploaded) this pin is an output and indicates the status of the boot loader. Once firmware has
been loaded, the pin is available as a GPIO.
5. During normal operation, this pin
must
be tied to ground (recommended) or left open.
6. If the modem is not loading the firmware from an external SPI memory, it is recommended that this pin is tied to ground or Vdd.
7. During normal operation, it is recommended that this pin is tied to ground.
8. During normal operation, this pin must be tied to Vdd.
9. If a general purpose IO is configured as an output, the pull−down resistor is disconnected.
SDI
SCK
RXD
IO9
TXD
VDD
VSS
VDD1V8
XOUT
XIN
DATA/PRES
EXT_CLK_E
IO7
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