CY2XF32
High Performance CMOS Oscillator with
Frequency Margining – Pin Control
High Performance CMOS Oscillator with Frequency Margining – Pin Control
Features
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Functional Description
The CY2XF32 is a high performance and high frequency crystal
oscillator (XO). It uses a Cypress proprietary low noise PLL to
synthesize the frequency from an integrated crystal. The output
frequency can be changed via two select pins, allowing easy
frequency margin testing in applications.
The CY2XF32 is available as a factory configured device or as
a field programmable device.
For a complete list of related documentation,
click here.
Crystal oscillator with CMOS output
Output frequency from 8 MHz to 200 MHz
Two frequency margining control pins (FS0, FS1)
Output enable or power-down function
Factory configured or field programmable
Integrated phase-locked loop (PLL)
Supply voltage: 3.3 V or 2.5 V
Pb-free package: 5.0 × 3.2 mm LCC
Commercial and industrial temperature ranges
Logic Block Diagram
CRYSTAL
OSCILLATOR
LOW -NOISE
PLL
OUTPU T
DIVIDER
4
CLK
FS1
2
FREQUENCY
SELECT DECODE
FS0
5
OE/PD#
1
Cypress Semiconductor Corporation
Document Number: 001-53147 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 14, 2014
CY2XF32
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 3
Programming Description ............................................... 4
Field Programmable CY2XF32F ................................. 4
Factory Configured CY2XF32 ..................................... 4
Programming Variables ................................................... 4
Output Frequencies ..................................................... 4
Pin 1: Output Enable or Power-down (OE/PD#) ......... 4
Supply Voltage ............................................................ 4
Industrial versus Commercial Device Performance .... 4
Absolute Maximum Conditions ....................................... 5
Operating Conditions ....................................................... 5
DC Electrical Characteristics .......................................... 6
AC Electrical Characteristics .......................................... 7
Switching Waveforms ...................................................... 8
Ordering Information ........................................................ 9
Possible Configurations ............................................... 9
Ordering Code Definitions ........................................... 9
Package Diagram ............................................................ 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC® Solutions ...................................................... 13
Cypress Developer Community ................................. 13
Technical Support ..................................................... 13
Document Number: 001-53147 Rev. *F
Page 2 of 13
CY2XF32
Pinouts
Figure 1. 6-pin Ceramic LCC pinout
OE/PD# 1
FS1 2
VSS 3
6 VDD
5 FS0
4 CLK
Pin Definitions
6-pin Ceramic LCC
Pin No.
1
2, 5
4
6
3
Pin Name
OE/PD#
FS1, FS0
CLK
VDD
VSS
I/O Type
Description
CMOS Input Output Enable or Power-down: Functionality is a programming option; see
Table 2
and
Table 3
for details.
CMOS Input Frequency Select.
CMOS Output Clock Output.
Power
Power
Supply Voltage: 2.5 V or 3.3 V.
Ground.
Pin 1 is programmed to function as either OE (output enable) or
PD# (power-down, active low). The OE function is used to enable
or disable the CLK output very quickly, but it does not reduce
core power consumption. The PD# function puts the device into
a low power state, but the wake up takes longer because the PLL
must reacquire lock. Details are shown in
Table 2
and
Table 3.
Table 2. Output Enable Operation
OE
Output Frequency
Frequency 0
Frequency 1
Frequency 2
Frequency 3
Table 3. Power-down Operation
PD#
0
1
PLL & Xtal Oscillator
Off
Active
Output Buffer
Off
On
0
1
PLL & Xtal Oscillator
Active
Active
Output Buffer
Off
On
Functional Overview
The FS0 and FS1 pins select between four different output
frequencies, as shown in
Table 1.
Frequency margining is a
common application for this feature. One frequency is used for
the standard operating mode of the device, while the other
frequencies are available for margin testing, either during
product development or in system manufacturing test.
Table 1. Frequency Select
FS1
0
0
1
1
FS0
0
1
0
1
When changing the output frequency, the frequency transition is
not guaranteed to be smooth. There can be frequency
excursions beyond the start frequency and the new frequency.
Glitches and runt pulses are possible, and time must be allowed
for the PLL to relock.
Document Number: 001-53147 Rev. *F
Page 3 of 13
CY2XF32
Programming Description
The CY2XF32 is a programmable device. Before being used in
an application, it must be programmed with the output
frequencies and other variables described in a later section. Two
different device types are available, each with its own
programming flow. They are described below.
Programming Variables
Output Frequencies
The CY2XF32 is programmed with up to four independent output
frequencies, which are then selected using the FS0 and FS1
pins. The device can synthesize frequencies to a resolution of
one part per million (ppm), but the actual accuracy of the output
frequency is limited by the accuracy of the integrated reference
crystal.
Field Programmable CY2XF32F
Field programmable devices are shipped unprogrammed and
must be programmed before being installed on a printed circuit
board (PCB). Customers use CyberClocks™ Online Software to
specify the device configuration and generate a JEDEC
(extension .jed) programming file. Programming of samples and
prototype quantities is available using a Cypress programmer.
Third party vendors manufacture programmers for small to large
volume applications. Cypress’s value added distribution partners
also provide programming services. Field programmable
devices are designated with an “F” in the part number. They are
intended for quick prototyping and inventory reduction. The
CY2XF32 is one time programmable (OTP).
The software is located at
www.cyberclocksonline.com.
Pin 1: Output Enable or Power-down (OE/PD#)
Pin 1 is programmed as either Output Enable (OE) or
Power-down (PD#).
Supply Voltage
A programming option optimizes the CY2XF32 for either 2.5 V
or 3.3 V supply voltage. A device programmed for a particular
supply voltage is not guaranteed to meet specifications when
operated at the other voltage.
Industrial versus Commercial Device Performance
Industrial and commercial devices have different internal
crystals. This has a potentially significant impact on performance
levels for applications requiring the lowest possible phase noise.
CyberClocks Online Software displays expected performance
for both options.
Table 4. Device Programming Variables
Variable
Output Frequency 0 (Power on default)
Output Frequency 1
Output Frequency 2
Output Frequency 3
Pin 1 Functionality (OE or PD#)
Supply Voltage (2.5 V or 3.3 V)
Temperature Range (Commercial or Industrial)
Factory Configured CY2XF32
For ready-to-use devices, the CY2XF32 is available with no field
programming required. All requests are submitted to the local
Cypress Field Application Engineer (FAE) or sales
representative. After the request is processed, the user receives
a new part number, samples, and data sheet with the
programmed values. This part number is used for additional
sample requests and production orders.
Document Number: 001-53147 Rev. *F
Page 4 of 13
CY2XF32
Absolute Maximum Conditions
Parameter
V
DD
V
IN[1]
T
S
T
J
ESD
HBM
JA[2]
Description
Supply Voltage
Input Voltage, DC
Temperature, Storage
Temperature, Junction
ESD Protection (Human Body
Model)
JEDEC STD 22-A114-B
Relative to V
SS
Non operating
Condition
Min
–0.5
–0.5
–55
–40
2000
64
Max
4.4
V
DD
+ 0.5
135
135
–
Unit
V
V
C
C
V
C/W
Thermal Resistance, Junction to 0 m/s airflow
Ambient
Operating Conditions
Parameter
V
DD
T
PU
T
A
C
LOAD
3.3 V Supply Voltage Range
2.5 V Supply Voltage Range
Power-up Time for V
DD
to Reach Minimum Specified Voltage (Power
Ramp is Monotonic)
Ambient Temperature, Commercial
Ambient Temperature, Industrial
Load Capacitance at CLK (>100 MHz)
Load Capacitance at CLK (100 MHz)
Description
Min
3.135
2.375
0.05
0
–40
–
–
Typ
3.3
2.5
–
–
–
–
–
Max
3.465
2.625
500
70
85
10
15
Unit
V
V
ms
C
C
pF
pF
Notes
1. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has four layers of copper (2/1/1/2 oz.). The internal layers
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
Document Number: 001-53147 Rev. *F
Page 5 of 13
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