IDT70V3389S
HIGH-SPEED 3.3V 64K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
◆
Pipelined output mode
◆
Counter enable and reset features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
◆
◆
◆
◆
◆
◆
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP),
208-pin fine pitch Ball Grid Array, and 256-pin Ball
Grid Array
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
R/W
L
B
W
0
L
B
W
1
L
B
W
1
R
B
W
0
R
UB
R
LB
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
64K x 18
MEMORY
ARRAY
I/O
0 L
- I/O
1 7 L
CLK
L
Din_L
Din_R
I/O
0R
- I/O
17R
CLK
R
A
15L
A
0L
CNTRST
L
ADS
L
CNTEN
L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
15R
A
0R
CNTRST
R
ADS
R
CNTEN
R
4832 tbl 01
.
FEBRUARY 2018
1
©2018 Integrated Device Technology, Inc.
DSC 4832/14
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V3389 is a high-speed 64K x 18 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3389 has been
optimized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by
CE
0
and
CE
1,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
The 70V3389 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (V
DD
) remains at 3.3V.
Pin Configuration
(1,2,3,4)
1
12/12/01
2
NC
3
V
SS
4
NC
5
NC
6
NC
7
A
12L
8
A
8L
9
NC
10 11
V
DD
CLK
L
12
CNTEN
L
13 14
A
4L
A
0L
15
OPT
L
16 17
NC
V
SS
I/O
9L
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
V
SS
NC
V
SS
NC
A
13L
A
9L
NC
CE
0L
V
SS
ADS
L
A
5L
A
1L
V
SS
V
DDQR
I/O
8L
NC
V
DDQL
I/O
9R
V
DDQR
V
DD
NC
A
14L
A
10L
UB
L
CE
1L
V
SS
R/W
L
A
6L
A
2L
V
DD
I/O
8R
NC
V
SS
NC
V
SS
I/O
10L
NC
A
15L
A
11L
A
7L
LB
L
V
DD
OE
L
CNTRST
L
A
3L
V
DD
NC
V
DDQL
I/O
7L
I/O
7R
I/O
11L
NC
V
DDQR
I/O
10R
I/O
6L
NC
V
SS
NC
V
DDQL
I/O
11R
NC
V
SS
V
SS
I/O
6R
NC
V
DDQR
NC
V
SS
I/O
12L
NC
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
DDQR
I/O
12R
70V3389BF
BF-208
(5)
208-Pin fpBGA
Top View
(6)
V
DD
NC
V
SS
I/O
5R
V
DDQL
V
DD
V
SS
V
SS
V
SS
V
DD
V
SS
V
DDQR
I/O
14R
V
SS
I/O
13R
V
SS
I/O
3R
V
DDQL
I/O
4R
V
SS
NC
I/O
14L
V
DDQR
I/O
13L
NC
I/O
3L
V
SS
I/O
4L
V
DDQL
NC
I/O
15R
V
SS
V
SS
NC
I/O
2R
V
DDQR
NC
V
SS
NC
I/O
15L
I/O
1R
V
DDQL
NC
I/O
2L
I/O
16R
I/O
16L
V
DDQR
NC
NC
NC
A
12R
A
8R
NC
V
DD
CLK
R
CNTEN
R
A
4R
NC
I/O
1L
V
SS
NC
V
SS
NC
I/O
17R
NC
NC
A
13R
A
9R
NC
CE
0R
V
SS
ADS
R
A
5R
A
1R
V
SS
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
V
SS
NC
A
14R
A
10R
UB
R
CE
1R
V
SS
R/W
R
A
6R
A
2R
V
SS
NC
V
SS
NC
V
SS
NC
V
DD
NC
A
15R
A
11R
A
7R
LB
R
V
DD
OE
R
CNTRST
R
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4832 tbl 02
6.42
2
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3,4)
(con't.)
70V3389BC
BC-256
(5)
256-Pin BGA
Top View
(6)
12/12/01
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
B1
NC
B2
NC
B3
NC
B4
A
14L
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
CNTEN
L
B10
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
NC
C3
NC
C4
A
15L
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
CNTRST
L
C9
C10
C11
A
4L
C12
A
1L
C13
V
DD
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
NC
D4
A
13L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
CLK
L
ADS
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
V
DD
E4
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
F15
I/O
7R
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
G3
G4
V
DD
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
G12
V
DDQR
I/O
6R
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
H3
V
DDQR
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
5L
H13
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
DDQR
I/O
4R
I/O
3R
K13
K14
K15
I/O
4L
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
L13
NC
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
M3
M4
V
DD
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
V
DD
P4
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P5
P6
P7
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
R2
NC
R3
NC
R4
A
13R
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
R9
CLK
R
ADS
R
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
NC
T3
NC
T4
A
15R
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
CNTRST
R
T9
T10
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
NC
NC
NC
A
14R
A
11R
A
8R
NC
CE
1R
OE
R
CNTEN
R
A
5R
A
2R
A
0R
NC
NC
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
4832 drw 02c
,
6.42
3
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
12/12/01
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
UB
L
LB
L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
CLK
L
OE
L
R/W
L
ADS
L
CNTEN
L
CNTRST
L
A
6L
A
5L
A
4L
A
3L
A
2L
Pin Configuration
(1,2,3,4)
(con't.)
A
14L
A
15L
V
SS
NC
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
NC
NC
A
15R
A
14R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
70V3389PRF
PK-128
(5)
128-Pin TQFP
Top View
(6)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
A
1L
A
0L
OPT
L
NC (V
SS
)
(7)
IO
8L
IO
8R
NC (V
SS
)
(7)
V
SS
V
DDQL
IO
7L
IO
7R
V
SS
V
DDQR
IO
6L
IO
6R
IO
5L
IO
5R
V
DD
V
DD
V
SS
V
SS
IO
4R
IO
4L
IO
3R
IO
3L
IO
2R
IO
2L
V
SS
V
DDQL
IO
1R
IO
1L
V
SS
V
DDQR
IO
0R
IO
0L
OPT
R
A
0R
A
1R
4832 drw 02a
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NOTES:
1. All V
DD
pins must be connected to 3.3V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 14mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. In the 70V3379 (32K x 18) and 70V3389 (64K x 18), pins 96 and 99 are NC. The upgrade devices 70V3399 (128K x 18) and 70V3319 (256K x 18) assign
these pins as V
SS
. Customers who plan to take advantage of the upgrade path should treat these pins as V
SS
on the 70V3379 and 70V3389. If no upgrade is
needed, the pins can be treated as NC.
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
UB
R
LB
R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
CLK
R
OE
R
R/W
R
ADS
R
CNTEN
R
CNTRST
R
A
6R
A
5R
A
4R
A
3R
A
2R
.
6.42
4
IDT70V3389S
High-Speed 64K x 18 3.3V Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
15L
I/O
0L
- I/O
17L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
UB
L
- LB
L
V
DDQL
OPT
L
V
DD
V
SS
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
15R
I/O
0R
- I/O
17R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
UB
R
- LB
R
V
DDQR
OPT
R
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Address Strobe Enable
Counter Enable
Counter Reset
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)
(1)
Option for selecting V
DDQX
(1,2)
Power (3.3V)
(1)
Ground (0V)
4832 tbl 01
Names
NOTES:
1. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX
must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
Truth Table I—Read/Write and Enable Control
(1,2,3)
OE
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
CE
0
L
L
L
L
L
L
L
L
CE
1
H
H
H
H
H
H
H
H
UB
H
H
L
L
H
L
L
L
LB
H
L
H
L
L
H
L
L
R/W
X
L
L
L
H
H
H
X
Upper Byte
I/O
9-18
High-Z
High-Z
D
IN
D
IN
High-Z
D
OUT
D
OUT
High-Z
Lower Byte
I/O
0-8
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
D
OUT
High-Z
All Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
Outputs Disabled
4832 tbl 02
MODE
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
6.42
5
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