74AC273, 74ACT273 — Octal D-Type Flip-Flop
January 2008
74AC273, 74ACT273
Octal D-Type Flip-Flop
Features
■
Ideal buffer for microprocessor or memory
■
Eight edge-triggered D-type flip-flops
■
Buffered common clock
■
Buffered, asynchronous master reset
■
See 377 for clock enable version
■
See 373 for transparent latch version
■
See 374 for 3-STATE version
■
Outputs source/sink 24mA
■
74ACT273 has TTL-compatible inputs
General Description
The AC273 and ACT273 have eight edge-triggered
D-type flip-flops with individual D-type inputs and Q
outputs. The common buffered Clock (CP) and Master
Reset (MR) input load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each
D-type input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-
flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output
only is required and the Clock and Master Reset are
common to all storage elements.
Ordering Information
Order Number
74AC273SC
74AC273SJ
74AC273MTC
74AC273PC
74ACT273SC
74ACT273SJ
74ACT273MTC
Package
Number
M20B
M20D
MTC20
N20A
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
74AC273, 74ACT273 — Octal D-Type Flip-Flop
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
MR
CP
Q
0
–Q
7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
Mode Select-Function Table
Inputs
Operating Mode
Reset (Clear)
Load ‘1'
Load ‘0'
Outputs
D
n
X
H
L
MR
L
H
H
CP
X
Q
n
L
H
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
2
74AC273, 74ACT273 — Octal D-Type Flip-Flop
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
∆
V /
∆
t
∆
V /
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, AC Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate, ACT Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
3
74AC273, 74ACT273 — Octal D-Type Flip-Flop
DC Electrical Characteristics for AC
T
A
=
+25°C
Symbol
V
IH
T
A
=
–40°C to +85°C
Units
V
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
µA
mA
mA
µA
V
V
V
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
Guaranteed Limits
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
IN
=
V
IL
or V
IH
,
I
OH
=
–12mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(1)
0.002
0.001
0.001
V
IN
=
V
IL
or V
IH
,
I
OL
=
12mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
I
OUT
=
50µA
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
I
IN(2)
I
OLD
I
OHD
I
CC(2)
Maximum Input
Leakage Current
Minimum Dynamic
Output Current
(3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
4.0
40.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
3. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
4
74AC273, 74ACT273 — Octal D-Type Flip-Flop
DC Electrical Characteristics for ACT
T
A
=
+25°C
Symbol
V
IH
V
IL
V
OH
T
A
=
–40°C to +85°C
Units
V
V
V
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
1.5
75
–75
µA
mA
mA
mA
µA
V
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW
Level Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
V
IN
=
V
IL
or V
IH
,
I
OH
=
–24mA
(4)
I
OUT
=
50µA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
V
IN
=
V
IL
or V
IH
,
I
OL
=
24mA
(4)
V
I
=
V
CC
, GND
V
I
=
V
CC
– 2.1V
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
Typ.
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
Guaranteed Limits
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
0.6
V
OL
Maximum LOW
Level Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current
(5)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
4.0
40.0
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
©1988 Fairchild Semiconductor Corporation
74AC273, 74ACT273 Rev. 1.6.0
www.fairchildsemi.com
5
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