Si5017
OC-48/STM-16 SONET/SDH CDR IC
WITH
L
IMITING
A
MPLIFIER
Features
H
igh-speed clock and data recovery device with integrated limiting amplifier:
Supports OC-48/STM-16 and
Loss-of-signal level alarm
2.7 Gbps FEC
Data slicing level control
DSPLL
®
technology
10 mV
PP
differential sensitivity
Jitter generation 3.0 mUI
rms
(typ)
3.3 V supply
Small footprint: 5 x 5 mm
Reference and reference-less
operation supported
Ordering Information:
See page 22.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Pin Assignments
Si5017
BER_ALM
CLKOUT+
DIN–
CLKOUT–
21 VDD
20 REXT
19 RESET/CAL
18 VDD
17 DOUT+
16 DOUT–
15 TDI
8
LTR
9
LOS
10 11 12 13 14
DSQLCH
DIN+
VDD
VDD
CLKDSBL
BER_LVL
VDD
Description
The Si5017 is a fully-integrated, high-performance limiting amplifier (LA)
and clock and data recovery (CDR) IC for high-speed serial
communication systems. It derives timing information and data from a
serial input at OC-48 and STM-16 rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL® technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
The Si5017 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
VDD
VDD
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
1
2
3
4
5
6
7
NC
28 27 26 25 24 23 22
GND
Pad
Functional Block Diagram
LOS_LVL
LOS
Signal
Detect
Retim er
DSQLCH
BUF
2
DOUT+
DOUT–
DIN+
DIN–
2
Lim iting
Am p
DSPLL
BER
Monitor
BUF
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
Bias Gen.
Reset/
Calibration
BER_ALM
REXT
RESET/CAL
SLICE_LVL
LTR
BER_LVL
LOL
Rev. 1.5 6/08
Copyright © 2008 by Silicon Laboratories
Si5023
Si5017
T
ABLE O F
C
ONTENTS
Section
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.2. DSPLL
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.5. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.6. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.7. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.8. Bit-Error-Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.9. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.10. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.11. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.12. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.13. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.14. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.15. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.16. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.17. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.18. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5. Pin Descriptions: Si5017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3
Rev. 1.5
Si5017
1. Detailed Block Diagram
LOS
BER_LVL
BER_ALM
LTR
DSQLCH
LOS_LVL
Signal
Detect
BER
Monitor
Retime
DOUT+
DOUT–
DIN+
Limiting
Amp
Phase
Detector
A/D
DSP
n
VCO
CLK
Dividers
CLKOUT+
CLKOUT–
DIN+
SLICE_LVL
Slicing
Control
Lock
Detection
CLKDSBL
REFCLK±
(optional)
Bias
Generation
LOL
REXT
Calibration
RESET/CAL
4
Rev. 1.5
Si5017
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5017 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
3.135
Typ
25
3.3
Max
1
85
3.465
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5017 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of the "3. Typical Application Schematic" on page 11.
V
SIG NAL+
SIG NAL–
V
IS
t
A. Operation with Single-Ended Inputs
V
SIGNAL+
SIGNAL–
0.5 V
ID
(SIGNAL+) – (SIG NAL–)
V
ID
t
B. O peration with Differential Inputs and Outputs
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
Cf-D
DOUT
t
C r-D
CLK OUT
Figure 2. Clock to Data Timing
Rev. 1.5
5
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