CCD Linear Image Sensor
MN3674
Color CCD Linear Image Sensor
with 512 Pixels for R and B Colors/1024 Pixels for G Color
s
Overview
The MN3674 is a high responsivity CCD color linear image sensor
with 512 pixels each for R and B and 1024 G pixels, and having low
dark output floating photodiodes in the photodetector region and
CCD analog shift registers for read out.
It can read a 64mm-width color document with a high quality and a
maximum pseudo resolution of 400dpi. In addition to being used as a
color sensor, this device can also be used as a black and white sensor
if only the G row is used, and in this case, it is possible to read a
64mm-width document with a full resolution of 400dpi. Since a one
line delay analog memory is built in so as to compensate for the
difference in the positions of reading out between the R, B rows and
the G row, the configuration of the signal processing circuit becomes
simpler.
s
Pin Assignments
1
NC
NC
OS
1
DS
1
V
SS
ø
R
ø
1
ø
SG1
V
SS
V
SS
NC
1
2
3
4
5
6
7
8
9
10
11
1024
(Top View)
C26
22
21
20
19
18
17
16
15
14
13
12
NC
NC
OS
2
DS
2
V
DD
NC
ø
2
ø
SG2
ø
V
NC
NC
s
Features
•
2048 floating photodiodes and n-channel buried type CCD shift
registers for read out are integrated in a single chip.
•
RGB primary colors type on chip color filters are used for color
separation.
•
In order to compensate for the distance between the photodiode
rows for the R, B colors and the G color, the device has a built in
analog memory that can store the signals of one line of the R-B
colors row.
•
All clock inputs can be driven by 5V CMOS logic.
•
Use of photodiodes with a new structure has made the dark output
voltage very low.
•
Large signal output of typically 0.8V at saturation can be obtained.
WDIP022-G-0470B
s
Application
•
Color graphic read out in color image scanners, color fax machines,
etc.
CCD Linear Image Sensor
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Block Diagram
OS
2
20
MN3674
DS
2
19
V
DD
18
ø
2
16
ø
SG2
15
ø
V
14
1
12
1212
121212121212
121212121
1-line delay analog memory
B2 B4
B1 B3
12
1212
B32
D2 D4
R1 B1 R2
B31
D1 D3 G1 G2 G3
121212121212
R
B
512 512
D6 D8
G G
1023 1024
D5 D7
121212121
1
D
B1 to B32 : Black reference pixels
D1 to D8 : Dummy invalid pixels
7
8
9
10
3
4
5
6
OS
1
DS
1
V
SS
ø
R
ø
1
ø
SG1
V
SS
V
SS
s
Absolute Maximum Ratings (Ta=25˚C, V
SS
=0V)
Parameter
Power supply voltage
Input pulse voltage
Operating temperature range
Storage temperature range
Symbol
V
DD
V
I
T
opr
T
stg
Rating
– 0.3 to + 15
– 0.3 to + 15
0 to + 60
–25 to + 85
Unit
V
V
˚C
˚C
s
Operating Conditions
•
Voltage conditions (Ta=0 to + 60˚C, V
SS
=0V)
Parameter
Power supply voltage
CCD shift register clock High level
CCD shift register clock Low level
Vertical transfer clock High level
Vertical transfer clock Low level
Shift gate clock High level
Shift gate clock Low level
Reset gate clock High level
Reset gate clock Low level
Symbol
V
DD
V
ø H
V
ø L
V
VH
V
VL
V
SH
V
SL
V
RH
V
RL
(ø
1
, ø
2
)
(ø
V
)
(ø
SG1
, ø
SG2
)
(ø
R
)
Condition
min
11.4
4.5
0
4.5
0
4.5
0
4.5
0
typ
12.0
5.0
0.2
5.0
0.2
5.0
0.2
5.0
0.2
max
13.0
V
DD
0.5
V
DD
0.5
V
DD
0.5
V
DD
0.5
Unit
V
V
V
V
V
V
V
V
V
MN3674
•
Timing conditions (without 1-line delay operation) (Ta=0 to + 60˚C)
Parameter
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock pulse width
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 set up time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Shift clock 2 hold time
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
Symbol
f
C
f
R
t
Cr
t
Cf
t
Vr
t
Vf
t
VW
t
SG1r
t
SG1f
t
SG1s
t
SG1w
t
SG2r
t
SG2f
t
SG2s
t
SG2w
t
SG2h
t
Rr
t
Rf
t
Rs
t
Rw
t
Rh
See drive timing diagram (3)
See drive timing diagram (1)
See drive timing diagram (1)
Condition
See drive timing diagram (3) f
C
=1/2T
See drive timing diagram (3) f
R
=1/2T
See drive timing diagram (3)
ø
SG1
and ø
V
should be the same timing.
See drive timing diagram (1)
CCD Linear Image Sensor
min
0.1
0.1
0
0
0
0
5
0
0
0.5
5
0
0
0.5
5
0
0
0
0.7T
100
10
typ
1.0
1.0
20
20
15
15
10
15
15
1.0
10
15
15
1.0
10
1
10
10
—
200
125
max
3.0
3.0
50
50
50
50
50
50
50
2.0
50
50
50
2.0
50
2
20
20
—
—
—
Unit
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
•
Timing conditions (during 1-line delay operation) (Ta=0 to + 60˚C)
Parameter
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock set up time
Vertical transfer clock pulse width
Vertical transfer clock hold time
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
Symbol
f
C
f
R
t
Cr
t
Cf
t
Vr
t
Vf
t
Vs
t
Vw
t
Vh
t
SG1r
t
SG1f
t
SG1w
t
SG2r
t
SG2f
t
SG2s
t
SG2w
t
Rr
t
Rf
t
Rs
t
Rw
t
Rh
See drive timing diagram (3)
See drive timing diagram (2)
See drive timing diagram (2)
ø
SG1
and ø
V
should be the same timing.
See drive timing diagram (2)
Condition
See drive timing diagram (3) f
C
=1/2T
See drive timing diagram (3) f
R
=1/2T
See drive timing diagram (3)
min
0.1
0.1
0
0
0
0
0.5
5
0
0
0
5
0
0
0.5
5
0
0
0.7T
100
100
200
125
typ
1.0
1.0
20
20
15
15
1.0
10
1
15
15
10
15
15
1.0
10
10
10
max
3.0
3.0
50
50
50
50
2.0
50
2
50
50
50
50
50
2.0
50
20
20
—
—
—
Unit
MHz
MHz
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
CCD Linear Image Sensor
s
Electrical Characteristics
•
Clock input capacitance (Ta=–20 to + 60˚C)
Parameter
CCD Shift register clock input capacitance
Vertical transfer clock input capacitance
Reset clock input capacitance
Shift clock input capacitance
Symbol
C
1
, C
2
C
V
C
RS
C
SG1
, C
SG2
V
IN
=5V
f=1MHz
Condition
min
—
—
—
—
typ
200
100
20
100
MN3674
max
—
—
—
—
Unit
pF
pF
pF
pF
•
DC characteristics
Parameter
Power supply current
Symbol
I
DD
V
DD
= +12V
Condition
min
—
typ
10
max
20
Unit
mA
•
AC characteristics
Parameter
Signal output delay time
Symbol
t
OS
Condition
(a reference value)
min
—
typ
50
max
—
Unit
ns
s
Optical Characteristics
<Inspection conditions>
•
Ta=25˚C, V
DD
=12V, V
ø
H
=V
VH
=V
SH
=V
RH
=5V (pulse), f
C
=f
R
=1MHz, T
int
(accumulation time)=10ms
•
Light source: Daylight fluorescent lamp with IR/UV cutting filter
•
Optical system: A slit with an aperture dimensions of 20mm
×
20mm is used at a distance of 200mm from the sensor (equivalent
to F=10).
•
Load resistance = 100k Ohms
•
These specifications apply to the 512 valid R and G pixels and the 1024 valid G pixels excluding the dummy pixels D1 to D8.
Parameter
Responsivity
Photo response non-uniformity
Saturation output voltage
Saturation exposure
Symbol
R
R
R
G
R
B
PRNU
V
SAT
SE
R
SE
G
SE
B
V
DRK1
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Dynamic range
V
DRK2
DSNU
1
DSNU
2
STTE
DR
Note 7
Note 1
Note 1
Note 1
Note 2
Note 3
Note 4
Note 4
Note 4
OS1, Dark condition, see Note 5
OS2, Dark condition, see Note 5
OS1, Dark condition, see Note 6
OS2, Dark condition, see Note 6
Condition
min
0.70
1.40
0.90
—
650
0.67
0.36
0.53
—
—
—
—
92
—
typ
0.95
1.80
1.20
6
800
0.84
0.44
0.67
0.5
1.0
0.1
0.2
99
800
max
1.20
2.20
1.50
15
—
—
—
—
1.0
2.0
2.0
4.0
—
—
mV
mV
%
lx · s
%
mV
V/lx · s
Unit
Note 1) Responsivity (R)
This is the value obtained by dividing the average output voltage (V) of the all pixels by the exposure (lx· s).
The exposure (lx· s) is the product of the illumination intensity (lx) and the accumulation time (s).
Since the responsivity changes with the spectral distribution of the light source used, care should be taken when using a
light source other than the daylight type fluorescent lamp specified in the inspection conditions.
Note 2) Photo response non-uniformity (PRNU)
This is defined by the following equation where X
ave
is the average output voltage of the valid pixels of each of the colors
R, G, and B, and
∆x
is the difference between the output voltage of the maximum (or minimum) output pixel and X
ave
,
when the photodetector region is illuminated with light of a uniform illumination intensity distribution.
x
×100
(%)
PRNU=
X
ave
The incident light intensity shall be 50% of the standard saturation llight intensity.
MN3674
s
Optical Characteristics (continued)
CCD Linear Image Sensor
Note 3) Saturation output voltage:
This is the output voltage at the point beyond which it is not possible to maintain the linearity of the photoelectric
conversion characteristics as the exposure is increased. (The exposure at this point is called the saturation exposure.)
Note 4) Saturation Exposure (SE)
This is the exposure beyond which it is not possible to maintain the linearity of the output voltage as the exposure is
increased. When designing the equipment using these devices, make sure that the incident light exposure is set with
sufficient margin so that the CCD never gets saturated.
Note 5) Dark signal output voltage (V
DRK
)
This is defined as the average of the output from all the valid pixels in the dark condition at Ta=25˚C, T
int
=10ms.
Normally, the dark signal output voltage gets doubled for every 8 to 10˚C increase in Ta and is proportional to T
int
. The
dark signal output voltage (V
DRK2
) on the OS
2
side will be larger than the dark signal output voltage (V
DRK1
) on the OS
1
side because there is a delay memory on the OS
2
side.
Note 6) Dark signal non-uniformity (DSNU)
This is defined as the difference between the maximum value among the output voltages of the all valid pixels at
Ta=25˚Cand T
int
=10ms and V
DRK
.
V
DRK
DSNU
Note 7) Dynamic range (DR)
This is defined by the following equation.
DR= V
SAT
V
DRK
Since the dark signal output voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
s
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
NC
NC
OS
1
DS
1
V
SS
ø
R
ø
1
ø
SG1
V
SS
V
SS
NC
NC
NC
ø
V
ø
SG2
ø
2
NC
V
DD
DS
2
OS
2
NC
Pin name
Non connection
Non connection
Signal output 1
Compensation output 1
Ground
Reset clock
CCD clock (Phase 1)
CCD shift register clock 1
Ground
Ground
Non connection
Non connection
Non connection
Vertical transfer clock
Shift clock gate 2
CCD clock (Phase 2)
Non connection
Power supply
Compensation output 2
Signal output 2
Non connection
Red and Blue pixel output
Green pixel output
Condition
Non connection
NC
22
Note) Connect all NC pins externally to V
SS
(GND).
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