CCD Linear Image Sensor
MN3611RE
Color CCD Linear Image Sensor
with 720 Pixels each for R, G, and B Colors
s
Overview
The MN3611RE is a high responsivity CCD color linear image
sensor having low dark output floating photodiodes in the
photodetector region, CCD analog shift registers for read out, and 720
pixels each for the primary colors R, G, and B.
It can read a B6 size color document with a high quality and a
resolution of 170dpi.
s
Pin Assignments
1
OS
DS
V
DD
ø
R
NC
ø
1
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
2160
(Top View)
WDIP022-G-0470
22
21
20
19
18
17
16
15
14
13
12
V
SS
ø
SG
NC
ø
2
NC
NC
NC
NC
NC
NC
NC
s
Features
•
2160 (720
×
R.G.B) floating photodiodes and an n-channel buried
type CCD shift registers are built in a single chip.
•
It is possible to read a B6 size color document with a high quality
and a resolution of 170dpi.
•
RGB primary colors type on chip color filters are used for color
separation.
•
Very high responsivity is obtained because voltage amplifier
circuits are built in the chip.
•
Use of photodiodes with a new structure has made the dark output
voltage very low.
•
Large signal output of typically 2V at saturation can be obtained.
C20
s
Application
•
Reading out color images in a color scanner.
s
Block Diagram
V
SS
22
ø
SG
21
ø
2
19
2
Signal
output
amplifier
1
Compensation
output
amplifier
Clock
driver
1
2
3
4
1 21 21 2
B1
B2
B3
2 1 21 21 21 2 1
B 51
B 52
D1
D2
D3
1
2
3
4
5
1 21 2 1 21 2 1 21
2157
2158
2159
2160
D4
D5
D6
2
12121
1 21 21 21 21 2
21 21 21 21 21 2
B1 to B52 : Black reference pixels
D1 to D6 : Dummy invalid pixels
6
OS DS V
DD
ø
R
ø
1
CCD Linear Image Sensor
s
Absolute Maximum Ratings (Ta=25˚C, V
SS
=0V)
Parameter
Power supply voltage
Input voltage
Output voltage
Operating temperature range
Storage temperature range
Symbol
V
DD
V
I
V
O
T
opr
T
stg
Rating
– 0.3 to +15
– 0.3 to +15
– 0.3 to +15
–25 to + 60
–40 to +100
MN3611RE
Unit
V
V
V
˚C
˚C
s
Operating Conditions
•
Voltage conditions (Ta=–25 to +60˚C, V
SS
=0V)
Parameter
Power supply voltage
CCD shift register clock High level
CCD shift register clock Low level
Shift gate clock High level
Shift gate clock Low level
Reset gate clock High level
Reset gate clock Low level
Symbol
V
DD
V
ø H
V
ø L
V
SH
V
SL
V
RH
V
RL
Condition
min
11.4
4.5
0
4.5
0
4.5
0
typ
12.0
5.0
0.2
5.0
0.2
5.0
0.2
max
13.0
5.5
0.5
5.5
0.5
5.5
0.5
Unit
V
V
V
V
V
V
V
•
Timing conditions (Ta=–25 to +60˚C)
Parameter
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift regisster clock fall time
Shift clock (ø
SG
) rise time
Shift clock (ø
SG
) fall time
Shift clock set up time
Shift clock pulse width
Shift clock hold time
Reset clock rise time
Reset clock fall time
Reset clock pulse width
Reset clock hold time
Symbol
f
C
f
R
t
Cr
t
Cf
t
Sr
t
Sf
t
Ss
t
Sw
t
Sh
t
Rr
t
Rf
t
Rw
t
Rh
See input/output timing diagram.
See drive timing diagram.
See input/output timing diagram.
See drive timing diagram.
Condition
See drive timing diagram. f
C
=1/2T
See drive timing diagram. f
R
=1/T
See input/output timing diagram.
See drive timing diagram.
min
—
—
0
0
0
0
0
200
0
0
0
60
100
typ
0.5
1.0
60
60
50
50
100
1000
100
15
15
250
125
max
1.0
2.0
100
100
100
100
—
—
—
30
30
—
—
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Electrical Characteristics
•
Clock input capacitance (Ta=–25 to +60˚C)
Parameter
Shift register clock input capacitance
Reset clock input capacitance
Shift clock input capacitance
Symbol
C
ø1
,C
ø2
C
øR
C
øSG
f
reg
=1MHz
f
reg
=1MHz
f
reg
=1MHz
Condition
min
—
—
—
typ
350
15
130
max
400
30
200
Unit
pF
pF
pF
•
DC characteristics
Parameter
Power supply current
Symbol
I
DD
V
DD
=+12V
Condition
min
—
typ
8
max
15
Unit
mA
MN3611RE
•
AC characteristics
Parameter
Signal output delay time
Symbol
tos
Condition
CCD Linear Image Sensor
min
—
typ
100
max
—
Unit
ns
s
Optical Characteristics
<Inspection conditions>
•
Ta=25˚C, V
DD
=12V, V
ø
H
=V
SH
=V
RH
=5V (pulse), f
C
=0.5MHz, f
R
=1MHz, T
int
(accumulation time)=10ms
•
Light source: Daylight type fluorescent lamp with IR/UV cutting filter
•
Optical system: A slit with an aperture dimensions of 20mm
×
20mm is used at a distance of 200mm from the sensor (equivalent
to F=10).
•
Load resistance = 100k Ohms
•
These specifications apply to the 2160 valid pixels excluding the dummy pixels D1 to D6.
Parameter
red
Responsivity
green
blue
Photo response non-uniformity
Odd/even bit non-uniformity
Saturation output voltage
Saturation exposure
Dark signal output voltage
Dark signal output non-uniformity
Shift register total transfer efficiency
Output impedance
Dynamic range
Signal output pin DC level
Compensation output pin DC level
Symbol
R
R
R
G
R
B
PRNU
O/E
V
SAT
SE
V
DRK
DSNU
STTE
Z
O
DR
V
OS
V
DS
Note 5
Note 5
Note 6
Note 6
Note 1
Note 2
Note 3
Note 3
Note 4
Note 4
—
—
92
—
—
3.5
3.5
—
Condition
min
4.5
10.0
6.5
—
—
1.5
typ
7.2
13.5
9.6
—
—
2.0
0.13
0.8
0.2
99
—
2,500
4.5
4.5
50
max
9.9
17.0
12.7
15
3
—
—
2.0
3.0
—
1
—
6.0
6.0
100
V
V
mV
%
%
V
lx·s
mV
mV
%
kΩ
V/lx· s
Unit
Signal and compensation output pin DC level difference |V –V
DS
|
OS
Note 1) The photo response non-uniformity (PRNU) for each color is defined by the following equation, where X
ave
is the average
output voltage of the 720 valid pixels and
∆x
is the absolute value of the difference between X
ave
and the voltage of the
maximum (or minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform
distribution over the entire surface.
x
×100
(%)
PRNU=
X
ave
The incident light intensity shall be 50% of the standard saturation light intensity.
Note 2) The odd/even bit non-uniformity (O/E) for each color is defined by the following equation, where X
ave
is the average
output voltage of the 720 valid pixels for each color and Xn is the output voltage of the ‘n’th pixel for each color, when the
surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface.
∑
| Xn–Xn
+1
|
O/E=
n=1
×100
(%)
719
×
X
ave
The incident light intensity shall be 50% of the standard saturation light intensity.
Note 3) The Saturation output voltage (V
SAT
) is defined as the output voltage at the point when the linearity of the photoelectric
characteristics cannot be maintained as the incident light intensity is increased. [The light intensity of exposure at this
point is called the saturation exposure (SE).]
Note 4) The dark signal output voltage (V
DRK
) is defined as the average output voltage of the 2160 pixels in the dark condition at
Ta=25˚C and T
int
=10ms. Normally, the dark output voltage doubles for every 8 to 10˚C rise in Ta, and is proportional to
T
int
.
The dark signal output non-uniformity (DSNU) is defined as the difference between the maximum output voltage among
all the valid pixels and V
DRK
in the dark condition at Ta=25˚C and T
int
=10ms.
V
DRK
DSNU
719
CCD Linear Image Sensor
s
Optical Characteristics (continued)
Note 5) The dynamic range (DR) is defined by the following equation.
MN3611RE
V
SAT
V
DRK
Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the
accumulation time is shorter.
Note 6) The signal output pin DC level (V
OS
) and the compensation output pin DC level (V
DS
) are the voltage values shown in the
following figure.
DR=
OS
V
OS
V
SS
V
SS
Reset feed
through level
DS
V
DS
s
Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Symbol
OS
DS
V
DD
ø
R
NC
ø
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
ø
2
NC
ø
SG
V
SS
Signal output
Compensation output
Power supply
Reset clock
Non connection
CCD Shift clock gate
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
Non connection
CCD Shift clock gate
Non connection
Shift clock gate
Ground
Pin name
Condition
Note) Connect all NC pins externally to V
SS
.
MN3611RE
s
Construction of the Image Sensor
The MN3611RE can be made up of the three sections of—a)
photo detector region, b) CCD transfer region (shift register),
and c) output region.
a) Photo detector region
•
The photoelectric conversion device consists of an 11µm
floating photodiode and a 3µm channel stopper for each
pixel, and 2160 of these devices are linearly arranged side by
side at a pitch of 14µm.
•
The photo detector's windows are 14µm
×
14µm squares and
light incident on areas other than these windows is optically
shut out.
•
The photo detector is provided with 52 optically shielded
pixels (black dummy pixels) which serve as the black
reference.
b) CCD Transfer region (shift register)
•
The light output that has been photoelectrically converted is
CCD Linear Image Sensor
transferred to the CCD transfer for each odd and even pixel at
the timing of the shift clock (ø
SG
). The optical signal electric
charge transferred to this analog shift register is successively
transferred out and guided to the output region.
•
A buried type CCD that can be driven by a two phase clock
(ø
1
, ø
2
) is used for the analog shift register.
c) Output region
•
The signal charge that is transferred to the output region is
sent to the detector where impedance transformation is done
using two source follower stages.
•
The DC level component and the clock noise component not
containing optical signals are output from the DS pin.
•
By carrying out differential amplification of the two outputs
OS and DS externally, it is possible to obtain an output signal
with a high S/N ratio by reducing the clock noise, etc.
s
Timing Diagram
(1) I/O timing
Integration Time (Tint.)
ø
SG
ø
1
ø
2
ø
R
1 2 3 4
6 7 8 9 10 11 58 59 60 61 62 63 64 65 66
2222 2224 2226
2223 2225
DS
OS
1 2 3 4
6 7 8 B
1
B
2
B
50
B
51
B
52
2159
2160D
4
D
5
D
6
Note) Repeat the transfer
pulses (cp) for
more than 1114
periods.
Blank feed
(for 8 pixels)
Black reference
pixel signal
(for 52 pixels)
D
1
D
2
D
3
R
1
G
1
B
1
Valid pixel signal
(for 2160 pixels)
Invalid pixel signal
(for 3 pixels)
Invalid pixel signal
(for 3 pixels)
(2) Drive timing
t
Sr
t
Sf
90%
ø
SG
10%
90%
ø
1
t
Cr
ø
2
10%
t
Cf
90%
50%
10%
t
RS
90%
50%
10%
t
Rf
T
Reference level
90%
Signal output voltage
t
Rh
ø
R
90%
t
Rr
t
RW
ø
1
DS
t
Ss
t
SW
t
Sh
OS
t
OS
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