1.8 Volt Intel StrataFlash
®
Wireless
Memory with 3.0-Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
■
High performance Read-While-Write/Erase
— 85 ns initial access
— 52MHz with zero wait state, 17 ns clock-to-data
output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 10 µs/byte (Typ)
■
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Multiple 16-Mbit partitions: 256Mb devices
— Four 16-KWord parameter blocks: top or
bottom configurations
— 64K-Word main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
■
Power
— 1.7 V - 2.0 V V
CC
operation
— I/O voltage: 2.2 V - 3.3 V
— Standby current: 30 µA (Typ)
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— Automatic Power Savings (APS) mode
■
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel® Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
■
Security
— OTP space:
— 64 unique device identifier bits
— 64 user-programmable OTP bits
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: V
PP
= GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
■
Density and Packaging
— 64-, 128- and 256-Mbit density in VF BGA
packages
— 128/0, and 256/0 Density in Stacked-CSP
— 16-bit wide data bus
Intel StrataFlash
®
memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background.
The
1.8 Volt Intel StrataFlash
®
wireless memory with 3-Volt
I/O device is manufactured using Intel
0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging.
.
The 1.8 Volt Intel StrataFlash
®
wireless memory with 3-Volt
I/O product is the latest generation of
Notice:
This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251903-003
April 2003
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not
finalize a design with this information.
The 1.8 Volt Intel StrataFlash® Wireless Memory with 3.0 Volt I/O datasheet may contain design defects or errors known as errata which may cause
the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © 2003, Intel Corporation
* Other names and brands may be claimed as the property of others.
2
28F640L30, 28F128L30, 28F256L30
Contents
1.0
Introduction
..................................................................................................................7
1.1
1.2
1.3
Nomenclature ........................................................................................................7
Acronyms ..............................................................................................................7
Conventions ..........................................................................................................8
Product Overview ..................................................................................................9
Ballout Diagrams for VF BGA Package...............................................................10
Ballout Diagrams for Intel® Stacked Chip Scale Package ..................................11
Signal Descriptions for VF BGA Package ...........................................................12
2.4.1 Signal Descriptions for 128/0 and 256/0 Stacked-CSP..........................13
Memory Map .......................................................................................................15
2.0
Device Description
....................................................................................................9
2.1
2.2
2.3
2.4
2.5
3.0
Device Operations
...................................................................................................17
3.1
Bus Operations....................................................................................................17
3.1.1 Reads .....................................................................................................17
3.1.2 Writes .....................................................................................................17
3.1.3 Output Disable........................................................................................17
3.1.4 Standby ..................................................................................................18
3.1.5 Reset ......................................................................................................18
Device Commands ..............................................................................................18
Command Definitions ..........................................................................................20
Asynchronous Page-Mode Read ........................................................................22
Synchronous Burst-Mode Read ..........................................................................22
4.2.1 Burst Suspend........................................................................................23
Read Configuration Register (RCR)....................................................................23
4.3.1 Read Mode .............................................................................................24
4.3.2 Latency Count ........................................................................................24
4.3.3 WAIT Polarity .........................................................................................26
4.3.3.1 WAIT Signal Function................................................................26
4.3.4 Data Hold ...............................................................................................27
4.3.5 WAIT Delay ............................................................................................28
4.3.6 Burst Sequence......................................................................................28
4.3.7 Clock Edge .............................................................................................28
4.3.8 Burst Wrap .............................................................................................28
4.3.9 Burst Length ...........................................................................................29
Word Programming .............................................................................................30
5.1.1 Factory Word Programming ...................................................................31
Buffered Programming ........................................................................................31
Buffered Enhanced Factory Programming ..........................................................32
5.3.1 Buffered EFP Requirements and Considerations ..................................32
5.3.2 Buffered EFP Setup Phase ....................................................................33
5.3.3 Buffered EFP Program/Verify Phase......................................................33
3.2
3.3
4.0
Read Operations
.......................................................................................................22
4.1
4.2
4.3
5.0
Programming Operations
.....................................................................................30
5.1
5.2
5.3
3
28F640L30, 28F128L30, 28F256L30
5.4
5.5
5.6
5.3.4 Buffered EFP Exit Phase ....................................................................... 34
Program Suspend ............................................................................................... 34
Program Resume ................................................................................................ 35
Program Protection ............................................................................................. 35
6.0
Erase Operations
..................................................................................................... 36
6.1
6.2
6.3
6.4
Block Erase ......................................................................................................... 36
Erase Suspend.................................................................................................... 36
Erase Resume .................................................................................................... 37
Erase Protection.................................................................................................. 37
Block Locking ...................................................................................................... 38
7.1.1 Lock Block .............................................................................................. 38
7.1.2 Unlock Block .......................................................................................... 38
7.1.3 Lock-Down Block ................................................................................... 38
7.1.4 Block Lock Status................................................................................... 39
7.1.5 Block Locking During Suspend .............................................................. 39
Protection Registers ............................................................................................ 40
7.2.1 Reading the Protection Registers .......................................................... 41
7.2.2 Programming the Protection Registers .................................................. 42
7.2.3 Locking the Protection Registers ........................................................... 42
Memory Partitioning ............................................................................................ 43
Read-While-Write Command Sequences ........................................................... 43
8.2.1 Simultaneous Operation Details............................................................. 44
8.2.2 Synchronous and Asynchronous Read-While-Write
Characteristics and Waveforms ............................................................. 44
8.2.2.1 Write operation to asynchronous read transition....................... 44
8.2.2.2 Synchronous read to write operation transition ......................... 45
8.2.3 Read Operation During Buffered Programming Flowchart..................... 45
Simultaneous Operation Restrictions .................................................................. 46
Read Status Register .......................................................................................... 47
9.1.1 Clear Status Register ............................................................................. 48
Read Device Identifier ......................................................................................... 48
CFI Query............................................................................................................ 49
Power-Up/Down Characteristics ......................................................................... 50
Power Supply Decoupling ................................................................................... 50
Automatic Power Saving (APS) .......................................................................... 50
Reset Characteristics .......................................................................................... 50
Absolute Maximum Ratings ................................................................................ 52
Operating Conditions .......................................................................................... 52
DC Current Characteristics ................................................................................. 53
DC Voltage Characteristics ................................................................................. 54
7.0
Security Modes
......................................................................................................... 38
7.1
7.2
8.0
Dual-Operation Considerations
......................................................................... 43
8.1
8.2
8.3
9.0
Special Read States
................................................................................................ 47
9.1
9.2
9.3
10.0
Power and Reset
...................................................................................................... 50
10.1
10.2
10.3
10.4
11.0
Thermal and DC Characteristics
........................................................................ 52
11.1
11.2
11.3
11.4
4
28F640L30, 28F128L30, 28F256L30
12.0
AC Characteristics
...................................................................................................55
12.1
12.2
12.3
12.4
12.5
12.6
AC Read Specifications (VCCQ = 2.2 V – 3.3 V) ................................................55
AC Write Specifications.......................................................................................60
Program and Erase Characteristics ....................................................................64
Reset Specifications............................................................................................64
AC Test Conditions .............................................................................................65
Capacitance ........................................................................................................66
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Appendix F
Appendix G
Write State Machine (WSM)
...........................................................................67
Flowcharts
............................................................................................................74
Common Flash Interface
................................................................................83
Mechanical Information
...................................................................................93
Additional Information
.....................................................................................97
Ordering Information for VF BGA Package
............................................98
Ordering Information for S-CSP Package
...............................................99
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