Storage Temperature Range..............................-65°C to +150°C
Lead Temperature (soldering, 10s)...................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
(Note 1)
Junction-to-Case Thermal Resistance (θ
JC
....................42°C/W
Junction-to-Ambient Thermal Resistance (θ
JA
)
............. 206.3°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
IN
= 14V, T
A
= T
J
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
Operating Voltage Range
Supply Current
SWT Ramp Current
SRT Ramp Current
SWT/SRT Ramp Threshold
Voltage
RESET TIMER
Power-On Reset Input Threshold
Voltage
RESETIN Input Leakage Current
RESET
Output Low Voltage
RESET
Leakage Current
ENABLE
Output Low Voltage
ENABLE
Leakage Current
Minimum Reset Timeout Period
Reset Timeout Period
Maximum Reset Time Period
RESET
to
ENABLE
Delay
RESETIN to
RESET
Delay
V
PON
I
LPON
V
OLRST
I
LKGR
V
OLEN
I
LKGE
t
RESETmin
t
RESET
V
RESETIN
rising
V
RESETIN
falling
V
RESETIN
= 2V
RESET
asserted, I
SINK
= 1mA
V
IN
= 1.1V, I
SINK
= 160µA,
RESET
asserted
RESET
asserted, I
SINK
= 0.4mA
V
RESET
= 20V,
RESET
not asserted
ENABLE
asserted, I
SINK
= 5mA
V
ENABLE
= 14V,
ENABLE
not asserted
C
SRT
= 390pF (Note 3)
C
SRT
= 2000pF (Note 3)
0.1
1
5
116.09
1.5
1
0.1
0.4
1.135
1.115
1.255
1.235
0.1
0.9
0.4
0.4
µA
V
µA
ms
ms
ms
µs
µs
V
1.383
1.363
V
µA
SYMBOL
V
IN
I
IN
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
450
410
1.115
CONDITIONS
MIN
5.0
18
18
500
500
1.235
TYP
MAX
40.0
30
60
550
600
1.363
UNITS
V
µA
nA
nA
V
I
RAMP_SWT
V
SWT
= 1.0V
I
RAMP_SRT
V
SRT
= 1.0V
V
RAMP
t
RESETmax
C
SRT
= 47nF
t
REDL
t
RRDL
RESETIN falling below V
PON
to
RESET
falling edge
www.maximintegrated.com
Maxim Integrated
│
2
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Electrical Characteristics (continued)
(V
IN
= 14V, T
A
= T
J
= -40°C to +125°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 2)
PARAMETER
WATCHDOG TIMER
WDI Input Threshold
WDI Input Hysteresis
WDI Minimum Pulse Width
WDI Input Current
Minimum Watchdog Timeout
Period
Watchdog Timeout Period
Maximum Watchdog Timeout
Watchdog Window
WDI to
ENABLE
Output Delay
RESET
Pullup Resistor Supply
Voltage
ENABLE
Pullup Resistor Supply
Voltage
V
IH
V
IL
WDI
HYST
t
WDImin
I
WDI
t
WPmin
t
WP
t
WPmax
D
WDI
(Note 4)
WDI = 0 or 14V
C
SWT
= 680pF (Note 3)
C
SWT
= 1200pF (Note 3)
C
SWT
= 22nF
MAX16998B
MAX16998D
Start from WDI third wrong trigger
(Note 5)
(Note 5)
2.25
2.25
45
67.5
6.5
0.1
6.8
12
217.36
50
75
100
2.5
2.5
18.00
28.00
55
82.5
200
2.25
0.9
V
mV
µs
µA
ms
ms
ms
%t
WP
µs
V
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Note 2:
R
RESET
and R
ENABLE
are external pullup resistors for open-drain outputs. Connect R
RESET
and R
ENABLE
to a minimum
2.5V voltage. Connect R
RESET
to a maximum voltage of 18V and connect R
ENABLE
to a maximum voltage of 28V.
Note 3:
Calculated based on V
RAMP
= 1.235V and I
RAMP
= 500nA.
Note 4:
WDI pulses narrower than 1μs will be ignored. WDI pulses wider than 6.5μs will be recognized.
Note 5:
Not production tested, guaranteed by design.
Typical Operating Characteristics
(C
SWT
= C
SRT
= 1500pF, T
A
= +25°C, unless otherwise noted.)
MAX16997/98 toc01
MAX16997/98 toc02
I
RAMP
= 500nA
I
RAMP
= 500nA
SUPPLY CURRENT (µA)
1000
100
10
1
0.1
WATCHDOG TIMEOUT PERIOD (ms)
RESET TIMEOUT PERIOD (ms)
24
22
20
18
16
14
12
RESET
AND
ENABLE
NOT
ASSERTED
1000
100
10
0.1
1
10
C
SRT
(nF)
100
1000
1
0.1
1
10
C
SWT
(nF)
100
1000
10
0
10
20
30
40
50
SUPPLY VOLTAGE (V)
www.maximintegrated.com
Maxim Integrated
│
3
MAX16997/98 toc03
10,000
RESET TIMEOUT PERIOD
vs. C
SRT
10,000
WATCHDOG TIMEOUT PERIOD
vs. C
SWT
26
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Typical Operating Characteristics (continued)
(C
SWT
= C
SRT
= 1500pF, T
A
= +25°C, unless otherwise noted.)
MAX16997/98 toc04
MAX16997/98 toc05
RESETIN/EN THRESHOLD VOLTAGE (V)
19.5
SUPPLY CURRENT (µA)
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
1.33
1.30
1.28
1.25
1.23
1.20
1.18
1.15
1.13
1.10
FALLING
RISING
RESETIN/EN THRESHOLD VOLTAGE (V)
RESET
AND
ENABLE
NOT
ASSERTED
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
4
8
12
16
20
24
28
32
36
FALLING
RISING
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
40
SUPPLY VOLTAGE (V)
MAX16997/98 toc07
MAX16997/98 toc08
RESET/WATCHDOG TIMEOUT PERIOD (ms)
RESET/WATCHDOG TIMEOUT PERIOD (ms)
RESETIN TO
RESET
DELAY (ms)
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
RESETIN FROM 2V TO 0V
7
6
5
4
3
2
1
0
4
8
12
16
20
24
28
32
36
WATCHDOG TIMEOUT
PERIOD (C
SWT
= 680pF)
100
90
80
70
60
50
40
30
20
10
4
8
12
16
20
24
28
32
36
RESET TIMEOUT
PERIOD (C
SRT
= 10nF)
WATCHDOG TIMEOUT
PERIOD (C
SWT
= 10nF)
100mV OVERDRIVE
50mV OVERDRIVE
RESET TIMEOUT
PERIOD (C
SRT
= 680pF)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
40
40
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX16997/98 toc10
515
510
505
I
RAMP
(nA)
500
495
490
485
480
475
470
MAX16997/98 toc11
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
ENABLE
OUTPUT VOLTAGE (V)
RESET
OUTPUT VOLTAGE (V)
0.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0
5
10
15
20
25
30
SINK CURRENT (mA)
SINK CURRENT (mA)
www.maximintegrated.com
Maxim Integrated
│
4
MAX16997/98 toc12
520
I
RAMP
vs. TEMPERATURE
1.0
RESET
OUTPUT VOLTAGE
vs. SINK CURRENT
0.8
ENABLE
OUTPUT VOLTAGE
vs. SINK CURRENT
MAX16997/98 toc09
2.00
RESETIN TO
RESET
DELAY
vs. TEMPERATURE
8
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
110
RESETIN/WATCHDOG PERIOD
vs. SUPPLY VOLTAGE
MAX16997/98 toc06
20.0
SUPPLY CURRENT
vs. TEMPERATURE
1.35
RESETIN/EN THRESHOLD VOLTAGE
vs. TEMPERATURE
1.50
RESETIN/EN THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX16997/MAX16998
High-Voltage Watchdog Timers with
Adjustable Timeout Delay
Pin Configuration
PIN
MAX16997A
1
2
3, 7
4
5
MAX16998A/B/D
1
—
—
4
5
NAME
IN
EN
N.C.
SWT
GND
FUNCTION
Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.
High-Impedance Input to the Enable Comparator. Depending on the voltage level at
EN, the internal watchdog timer is turned on or off (see the
EN Input
section).
No Connection. Not internally connected.
Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and
GND to set the basic watchdog timeout period. Connect SWT to ground to disable
the watchdog timer function. See the
Selecting the Watchdog Timeout Capacitor
section.
Ground
Watchdog Input.
MAX16997A/MAX16998A (Timeout Watchdog):
Two consecutive WDI falling
edges must occur at WDI within the watchdog timeout period or
RESET
asserts.
The watchdog timer clears when a falling edge occurs on WDI or whenever
RESET
is asserted.
ENABLE
asserts if three consecutive watchdog timeout periods have
expired without a falling edge at WDI. WDI is a high-impedance input. Leaving WDI
unconnected will cause improper operation of the watchdog timer.
MAX16998B/D (Window Watchdog):
WDI falling transitions within periods shorter
than the closed window width or longer than the basic watchdog timeout period
force
RESET
to assert low for the reset timeout period. The watchdog timer begins
to count after
RESET
is deasserted. The watchdog timer clears when a WDI falling
edge occurs or whenever
RESET
is asserted.
ENABLE
asserts if three consecutive
watchdog timeout periods have expired without a falling edge at WDI. WDI is a
high-impedance input. Leaving WDI unconnected will cause improper operation of
the watchdog timer.
Open-Drain Enable Output.
ENABLE
asserts when three consecutive WDI faults
occur.
ENABLE
remains low until three consecutive good WDI falling edges occur.
ENABLE
does not assert if the voltage at RESETIN (EN) is below its threshold.
These devices are guaranteed to be in correct
ENABLE
output logic state when
V
IN
remains greater than 1.1V.
Reset Input. High-impedance input to the reset comparator. When V
RESETIN
falls
below 1.235V,
RESET
asserts.
RESET
remains asserted as long as V
RESETIN
is
low and for the reset timeout period after RESETIN goes high. Connect V
RESETIN
to the center point of an external resistive divider to set the threshold for the
externally monitored voltage. Connect RESETIN to a defined voltage logic-level.
Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND
to set the reset timeout period. See the
Selecting the Reset Timeout Capacitor
section.
Open-Drain Reset Output.
RESET
asserts whenever RESETIN drops below the
selected reset threshold voltage (V
PON
).
RESET
remains low for the reset timeout
period after all reset conditions are removed, and then goes high.
RESET
asserts
for a period of t
RESET
whenever a WDI fault occurs. Connect
RESET
to a pullup
resistor connected to a voltage higher than 2.5V (typ).
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
